Zach PfefferAug 8, 20212 minBoot the 2020.1 FSBL in QEMUThis write-up shows how to boot the 2020.1 FSBL in QEMU. It also shows how to recompile the FSBL from PetaLinux 2020.1.
Zach PfefferMay 16, 20212 minA List of the Compiled U-Boot .c Files in a 2019.1 PetaLinux ZCU102 BuildThis post lists all the c files compiled by default when a user builds U-Boot using PetaLinux Tools for the ZCU102. Producing the List...
Zach PfefferDec 1, 20201 minHow do I run Vivado 2019.1 from the command line on Linux?This post shows how to run Vivado 2019.1 from the command line. It also shows you how to run Vivado in non-GUI mode and in batch mode....
Zach PfefferApr 19, 201911 minGetting Started with Vivado High-Level Synthesis TranscriptThis is a transcript of the Xilinx Quick Take video Getting Started with Vivado High-Level Synthesis at [link]. Transcript Hello and...
Zach PfefferApr 14, 201911 minXilinx's "Creating an AXI Peripheral in Vivado": Transcript, Screenshots & CommentaryThis post presents a transcript + screenshots of "Creating an AXI Peripheral in Vivado" from Xilinx. It is intended to reinforce learning...
Zach PfefferApr 13, 20191 minZynq QSPI Flash Support Guide from XilinxThis post lists links to a QSPI Flash Support Guide that Xilinx released. It also presents a link to the guide in case the original link...
Zach PfefferApr 12, 20191 minWhat Should the Board Trace Delay Be if the Clock and Data Traces have the same Length?A good post about what board trace delay should be if the clock and data traces have the same length. "board trace delay in source...
Zach PfefferApr 12, 20191 minA Good Constraint ConversationThis Xilinx community forums link contains some good information on what's actually needed to constrain I/O (embedded in a conversation...
Zach PfefferFeb 21, 20192 minBare-Metal Application Boot from Flash on the Xilinx Zynq-7000 of the ZC702 This post lists how to create a complete bare-metal application that boots from the Micron Quad SPI and what happens during boot. The...