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    Boot the 2020.1 FSBL in QEMU
    Zach Pfeffer
    • Aug 8, 2021
    • 2 min

    Boot the 2020.1 FSBL in QEMU

    This write-up shows how to boot the 2020.1 FSBL in QEMU. It also shows how to recompile the FSBL from PetaLinux 2020.1.
    616 views0 comments
    A List of the Compiled U-Boot .c Files in a 2019.1 PetaLinux ZCU102 Build
    Zach Pfeffer
    • May 16, 2021
    • 2 min

    A List of the Compiled U-Boot .c Files in a 2019.1 PetaLinux ZCU102 Build

    This post lists all the c files compiled by default when a user builds U-Boot using PetaLinux Tools for the ZCU102. Producing the List...
    69 views0 comments
    How do I run Vivado 2019.1 from the command line on Linux?
    Zach Pfeffer
    • Dec 1, 2020
    • 1 min

    How do I run Vivado 2019.1 from the command line on Linux?

    This post shows how to run Vivado 2019.1 from the command line. It also shows you how to run Vivado in non-GUI mode and in batch mode....
    7,515 views0 comments
    Getting Started with Vivado High-Level Synthesis Transcript
    Zach Pfeffer
    • Apr 19, 2019
    • 11 min

    Getting Started with Vivado High-Level Synthesis Transcript

    This is a transcript of the Xilinx Quick Take video Getting Started with Vivado High-Level Synthesis at [link]. Transcript Hello and...
    413 views0 comments
    Xilinx's "Creating an AXI Peripheral in Vivado": Transcript, Screenshots & Commentary
    Zach Pfeffer
    • Apr 14, 2019
    • 11 min

    Xilinx's "Creating an AXI Peripheral in Vivado": Transcript, Screenshots & Commentary

    This post presents a transcript + screenshots of "Creating an AXI Peripheral in Vivado" from Xilinx. It is intended to reinforce learning...
    1,754 views0 comments
    Zynq QSPI Flash Support Guide from Xilinx
    Zach Pfeffer
    • Apr 13, 2019
    • 1 min

    Zynq QSPI Flash Support Guide from Xilinx

    This post lists links to a QSPI Flash Support Guide that Xilinx released. It also presents a link to the guide in case the original link...
    129 views0 comments
    What Should the Board Trace Delay Be if the Clock and Data Traces have the same Length?
    Zach Pfeffer
    • Apr 12, 2019
    • 1 min

    What Should the Board Trace Delay Be if the Clock and Data Traces have the same Length?

    A good post about what board trace delay should be if the clock and data traces have the same length. "board trace delay in source...
    42 views0 comments
    A Good Constraint Conversation
    Zach Pfeffer
    • Apr 12, 2019
    • 1 min

    A Good Constraint Conversation

    This Xilinx community forums link contains some good information on what's actually needed to constrain I/O (embedded in a conversation...
    26 views0 comments
    Bare-Metal Application Boot from Flash on the Xilinx Zynq-7000 of the ZC702
    Zach Pfeffer
    • Feb 21, 2019
    • 2 min

    Bare-Metal Application Boot from Flash on the Xilinx Zynq-7000 of the ZC702

    This post lists how to create a complete bare-metal application that boots from the Micron Quad SPI and what happens during boot. The...
    5,086 views0 comments

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