This post lists notes on the "Using the Vivado Timing Constraint Wizard" QuickTake Video from Xilinx. It includes info highlights, links to the video, further explanations of some terms used and the steps to use the Timing Constraint Wizard in Vivado.
Link to the Quick Take Video
Video at [link]
UltraFast Design Methodology
The UltraFast design methodology says (@ 2:09):
Define all the clocks that exist in your design
Then specify the interactions between these clocks
Next constraint all your inputs and outputs
And finally, cautiously and sparingly add timing exceptions such as: false paths and multicycle paths
Step 1: Run synthesis (the timing constraint wizard operates on a gate-level netlist)
Step 2: Run Sources > Hierarchy > Constraints > constrs_1 > dsp_block_constraints.xdc (to look at the existing constraints file)
Step 3: Run Synthesis > Synthesized Design > Report Timing Summary (to familiarize yourself with the design)
Step 4: Run Synthesis > Synthesized Design > Report Clock Interactions (to gain visibility into the clock domain crossings)
"Unsafe clock crossings" are in red.
Note from p.80 of UG906
A great CDC write can be found at [link]. The write up defines a CDC as: "A CDC signal is a signal latched by a flip-flop (FF) in one clock domain and sampled in another asynchronous clock domain." The write up also shows sync circuits.
@5:57 The narrator mentions that the sys_clk to clk_83 crossing has been constrained with the set_max_delay -datapath_only
@ 4:50 he brought this up in the existing .XDC file:
From the info below, this says that the maximum delay of a signal on the path from sys_clk (period 8.0) to clk_83 (period 12.00) should be a maximum of 8 ns.
How do you select 8 ns (how do you select the set_max_delay value)?
Short answer: it depends on the synchronizer circuit you're using. A longer answer can be found at [link] or here:
The clock crossing constraints [link].
More info on set_max_delay -datapath_only
Some more info on set_max_delay -datapath_only:
...and from p. 138:
...and (a good description):
There's also a QuickTake on this topic titled "Advanced Timing Exceptions False Path, Min Max Delay and Set ... at [link].
Constraining Inputs and Outputs
@ 3:45 the video talks about set_input_delay and set_output_delay
A whole video called, "Setting Input Delay" discusses setting input delay @ [link]
What is Input Delay?
From the video discussing input delay, Setting Input Delay, Input Delay is:
The maximum (for set up) and the minimum (for hold) "Clock to Out" + "Trace Delay"
...the video says we only need to set maximum input delay since the max is the only parameter that affects setup timing, we don't need to check our min before checking set up
...for hold timing, we need the min
If the "upstream device" is another FPGA we should be able to use the tools to figure out what the clock to output delay is. We can figure out the trace length delay from the board.
If this is a DDR interface, we need to to figure out the clock-to-out for the falling edge as well.
Additional Resources (@ 17:44)
Vivado courses @ https://xilinxprod-catalog.netexam.com/Training?searchCriteria=6995 (the link posted in the video is not longer live)
UG903: Using Constraints [2018.2 link]
UG906: Design Analysis and Closure Techniques [2018.2 link]
UG949: Ultrafast Design Methodology Guide for the Vivado Suite [2018.2 link]
More Resources not Called Out In Video
AN 433: Constraining and Analyzing Source-Synchronous Interfaces @ [link]