Resources to Learn How to Constrain Clocks and I/O

This post lists some resources that I found that have helped me learn about setting clock and I/O constraints.


The following present how to use Timing Analyzer + static timing analysis concepts like slack, input delay and output delay. They also provide a good overview of setting timing and I/O constraints:

  • Part 1: Timing Analyzer: Introduction to Timing Analysis [link]

  • Part 2: Timing Analyzer: Timing Analyzer GUI [link]

  • Part 3: Timing Analyzer: Intel Quartus Prime Integration & Reporting [link]

  • Part 4: Timing Analyzer: Required SDC Constraints [link]

I have pulled out posts that show each slide and list the transcripts at these four links:

  • Timing Analysis Concepts & Terminology [link] (part 1)

  • Fast & Slow Corners in Timing Analysis, Steps to Run Timing [link] (part 2)

  • Run Timing on a Cheaper Speed Grade to Save Money [link] (part 3)

  • SDC Design Constraint Examples and Explanations [link] (part 4)

In addition, Intel has these great courses that are free:

  • Constraining Source Synchronous Interfaces (OCSS1000) [link] [course]

  • Constraining Double Data Rate Source Synchronous Interfaces (ODDR1000) [link] [course]


  • Intel logo @ [link]

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