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XCVU9P-L2FLGA2104E Decode and Its Features


XCVU9P-L2FLGA2104E on a VCU118 Evaluation Kit

This post lists a XCVU9P-L2FLGA2104E decode and its features. This part is used on the AMD Virtex UltraScale+ FPGA VCU118 Evaluation Kit @ https://www.xilinx.com/products/boards-and-kits/vcu118.html.


XCVU9P-L2FLGA2104E Decode and Its Features


XC V U 9 P -L2 F L G A 2104 E

XC

Commercial Grade

V

Virtex

U

UltraScale   

9

Value Index

P

UltraScale+

-L2

Low Power

F

L

Lid SSI

G

RoHS 6/6 w/ Exemption 15

A

Package Designator

2104

Package Pin Count

E

Extended (Tj = 0 degC to +110 degC)

Virtex UltraScale+ FPGA Feature Summary


VU9P

System Logic Cells

2,586,150

CLB Flip-Flops

2,364,480

CLB LUTs

  1. 182,240

Max. Distributed RAM (Mb)

36.1

Block RAM Blocks

2,160

Block RAM (Mb)

75.9

UltraRAM Blocks

960

UltraRAM (Mb)

270

HBM DRAM (GB)

CMTs (1 MMCM and 2 PLLs)

30

Max. HP I/O(1)

832

Max. HD I/O(2)

0

DSP Slices

6,840

System Monitor

3

GTY Transceivers 32.75 Gb/s(3)

120

GTM Transceivers 58.0 Gb/s

0

100G / 50G KP4 FEC

0

Transceiver Fractional PLLs

60

PCIE4 (PCIe Gen3 x16)(4)

6

PCIE4C (PCIe Gen3 x16 / Gen4 x8)(4)(5)

0

150G Interlaken

9

100G Ethernet w/RS-FEC

9

(1) HP = High-performance I/O with support for I/O voltage from 1.0V to 1.8V.

(2) HD = High-density I/O with support for I/O voltage from 1.2V to 3.3V.

(3) GTY transceivers in the FLGF1924 package support data rates up to 16.3 Gb/s. See Table 14.

(4) Supported PCIe configurations are determined by transceiver count.

(5) This block operates in compatibility mode for 16.0 GT/s (Gen4) operation. Go to PG213, UltraScale+ Devices Integrated Block for PCI Express Product Guide, for details on compatibility mode.


Virtex UltraScale+ Device-Package Combinations and Maximum I/Os

Package (1)(2)(3)(4)(5)

Package Dimensions (mm)

VU9P



HP, GTY

FLGA2104

47.5x47.5

832, 52

FLGB2104

47.5x47.5

702, 76

FLGC2104

47.5x47.5

416, 104

FSGD2104

47.5x47.5

676, 76

FLGA2577

52.5x52.5

448, 120

(1) Go to Ordering Information for package designation details.

(2) All packages have 1.0 mm ball pitch.

(3) Packages with the same last letter and number sequence, e.g., A2104, are footprint compatible with all other UltraScale architecture-based devices with the same sequence. The footprint compatible devices within this family are outlined. See the UltraScale Architecture Product Selection Guide for details on inter-family migration.

(4) Consult UG583, UltraScale Architecture PCB Design User Guide for specific migration details.

(5) GTY transceivers in the FLGF1924 package support data rates up to 16.3 Gb/s.


Original Tables


References

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