Xilinx's "Creating an AXI Peripheral in Vivado": Transcript, Screenshots & Commentary

Updated: Apr 18, 2019

This post presents a transcript + screenshots of "Creating an AXI Peripheral in Vivado" from Xilinx. It is intended to reinforce learning how to create an AXI peripheral in Vivado and provide a reference to the steps presented. Corrections and tips have also been included to further aid learning. In addition, some screens have been zoomed and cropped to make certain actions more clear.

The original video can be found [here][YouTube].

You Will Learn How To:

  • Use the Create and Package IP feature of Vivado

  • Create an AXI slave that echos registers writes

  • Run the auto testbench to verify the IP

  • Import the IP into a Micro Blaze design

  • Test reads and writes from code running on the MicroBlaze using SDK

Transcript, Screenshots and Commentary

(00:03) Hello and welcome to this Vivado QuickTake video

Note: the title presented, "Packaging Custom IP for use with IP Integrator" does not line up with the title listed on the site hosting the video.

(0:08) In this video you'll learn how to create an AXI peripheral to which custom logic can be added to create a customer IP using the create and package IP feature of Vivado.

(0:21) This training assumes that you are familiar with designing IP subsystems in IP integrator. You can watch some of the quick take videos on IP Integrator as shown on this slide:

Note: here are the links to the videos:

(00:32) In this Quick Take video we'll create a new project in Vivado using the create and package IP feature, we will then create a slave AXI peripheral. We'll create a test-bench and necessary drivers for the peripheral for developing a software application in SDK. We'll simulate the AXI peripheral in Vivado to ensure that the registers of the AXI peripheral can be written and read from using an AXI bus functional simulation model. Then we'll create a MicroBlaze processor based system in which we will add this custom IP. The design will be then implemented and the bitstream will be generated. We'll then export the hardware to SDK and create a test application and generate an ELF. Finally, we'll launch our application on the target board: KC705 and verify its functionality.

(1:18) We start our design by launching Vivado and creating a new project from the Quick Start page. We'll name the project and specify the location where the project will be saved. We'll skip some of the other options for adding existing RTL IP constraints to the project at this time as everything needed for this project will be generated later.

Create a New Project

Step: click Create New Project

Step: click Next

Note: in the video the user taps Enter on the keyboard to go to the Next > screen

Step: enter a Project name, axi_peripheral in this case and click Next

Step: click Next

Step: click Next

Step: click Next

Step: click Next

(1:51) We select boards in the default part page. Vivado is board-aware and it knows the physical connections present on our target board. It can thus generate the appropriate physical and timing constraints where our target board based on the interfaces that we choose in our design, we select the KC705 target board here.

Step: click Boards

Step: click Kintex-7 KC705 Evaluation Platform

Step: click Next

(2:13) Lets review the summary screen to make sure that all the options have been entered correctly and click finish.

Step: click Finish

Output: the Create Project status bar pops up

Output: the Create Project pop-up shows Creating project...

Output: the Create Project pop-up shows: Initializing project...

(02:19) Once the project has been created, we launch the create and package IP feature. Using this feature, you can either package a new IP or you can create a custom AXI peripheral to which your logic can then be added to make your own custom IP.

Create and Package IP

Step: click Tools > Create and Package IP...

Step: click Next

(2:35) When you launch the create an IP package feature in a new project, you have two choices: (1) you either package a preexisting project directory or you can create a new AXI4 peripheral. We choose the creating a new AXI peripheral and click next.

Step: click Create a new AXI4 peripheral

Step: click Next

(2:53) In the next page we can specify a several options such as name, version, display name, description, and the location where the IP will be created. Once the IP is created, you can search for the IP in the IP catalog using the name given to this peripheral. Also note down the IP location. This is where the IP repository is created.

Step: click Next

(03:18) On the add interfaces page you choose the number of interfaces that you want the AXI peripheral to have. Interfaces can be added by clicking the plus sign and deleted by selecting the delete icon. Notice that the components symbol also gets updated as you add and delete interfaces. Several properties of the AXI4 peripheral can be specified on this page. You can specify the name of the AXI interface in the name field. You can choose the type of AXI4 protocol desired. The choices are light, full and stream. You can specify whether the interface is created in a master mode or a slave mode. You can also specify the data width for the interface and the number of registers desired. Currently the number of registers supported by this feature for AXI Lite interfaces between 4 to 512. For the purposes of this video, we'll go with the default values.

Demonstration of How to Add and Remove an AXI Interface (Not Required for These Steps)

Step: click + to add an interface

Output: a new AXI slave interface pops up after clicking +

Step: click X to remove an interface

Output: the new interface disappears after clicking the X to remove an interface

Output: pop up tool-tip text on Interface Type

Output: the Interface Type options: Lite, Full and Stream

Output: the Interface Mode options: Master and Slave

Output: the tool-tip text of Interface Type:

  • Lite : Simple, non-burst control register style interface

  • Full : Burst Capable, high-throughput memory mapped interface

  • Stream: Burst Capable, high-throughput streaming interface

Note: For more details on the AXI4 specification click here (TBD get link)

Output: the tool-tip text of Data Width (Bits)

(4:09) Click next to get to the by summary page...

Continue Creating and Packaging a New AXI Peripheral

Step: click Next

(4:10) ...where you can either add the IP to the repository or edit the IP further to create a custom IP. You can also create a test-bench to verify the AXI4 peripheral using an AXI bus functional simulation model or you can test the IP in hardware by using the JTAG-to-AXI IP core. In this case we will select the verify peripheral IP using AXI4 BFM simulation interface option...

Output: the default create a customer IP screen pops up

Step: click Verify peripheral IP using AXI4 BFM Simulation interface

(4:32) ...and click on finish to create the AXI peripheral.

Step: click Finish

Output: a Creating new peripheral... window pops up

(04:34) As you notice, a block design is created and an AXI peripheral is instantiated unconnected to the AXI bus functional model.

Output: a Opening BFM IPI demonstration design... status window pops up

Output: create_bd_design output on the Tcl Console

Output: the diagram starts to populate, ACLK, ARESETN and myip_0 are added

Output: the diagram continues to populate, master_0 is added

Output: ACLK is connected to m_axi_lite_aclk & s00_axi_aclk and ARESETN is connected to s00_axi_aresetn & m_axi_lite_aresetn

Output: additional Tcl Console output about /myip_0/S00_AXI/S00_AXI_reg being mapped into /master_0/Data_lite at 0x44A00000

Output: additional Tcl Console about VHDL and bd file for the BFM being written out.

Output: Create Peripheral pop-up reports: Generate IP 'myip_v1_0_bfm_1_myip_0_0'...

Output: Create Peripheral pop-up reports: Generate IP 'myip_v1_0_bfm_1_master_0_0'...

Output: Create Peripheral pop-up reports: Running xelab... (note: xelab is the simulator compiler. See [UG900] p.120 for more info)

Output: Create Peripheral pop-up reports: Launching simulation for 'myip_v1_0_tb_behav'...

Output: xsim starts to run

(05:01) The design is then elaborated and simulation is launched. The test-bench that is created with this design, exercises the bus functional model (BFM) to generate several read and write transactions. Those transactions can then be verified in the simulation window as well as on the Tcl console where the result of read/write transactions are written out.

Output: xsim running, current time reported.

Output: xsim done

How to Format Objects as Hex

Demo step: click a bus in the Objects window

Demo step: click Radix, Hexadecimal

Output: see the hex values in the Objects window

(5:23) Take a moment to look at the waveform window and also the TCL console to verify that write and read operations took place alright.

How to Format Signals as Hex

Step: select signals > select Radix > select Hexadecimal

Output: signals in hex

How to Zoom Fit

Step: TBD

Output: zoomed version

(5:35) You will notice several statements in the Tcl console showing the data written to the peripheral and the data read out from it.

Output: the Tcl console data