Help Debugging Embedded System, OS, and Driver Issues with 3rd-Party AMD Versal IP

AMD_logo

This post lists links to AMD Versal third-party IP details, including vendor, version, and accessible online manuals.

3rd-Party AMD Versal IP List

This is the complete 3rd-Party AMD Versal IP List. Vendor technical reference manuals (TRMs) have been listed if they were publically available. This table extends one @ “IP Block Versions” of the Versal ACAP Technical Reference Manual (AM011). Vendor TRMs have been cached at the Versal IP version.

IP Versions Zynq-7000 to Zynq UltraScale+ MPSoC to Versal : Versal Module Summary

Module Name Supplier Vendor IP Name Vendor IP Versions Xilinx TRM Vendor TRM Vendor Link
aes-gcm       https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/AES-GCM    
apu Arm MP054 r0p3-00rel0 https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/Application-Processing-Unit https://drive.google.com/file/d/15PlvTzBuECvnNJjs9jJEb5UzDEajQlBE/view?usp=share_link https://developer.arm.com/documentation/100095/0003/?lang=en
apu cache coherency Arm CCI-500 (PL442) r1p0-00rel0 https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/Cache-Coherent-Interconnect https://drive.google.com/file/d/1-8EC8eLo-DBjUeQ9MZqVnjXA-Mw3O7OY/view?usp=share_link https://developer.arm.com/documentation/100023/0100/?lang=en
apu crypto Arm MP005 r0p2-00rel0 https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/Cryptography-Engine https://drive.google.com/file/d/15NsaiCV83dT8qmcwUnks_w-cp4dVxnIp/view?usp=share_link https://developer.arm.com/documentation/100097/0002/?lang=en
apu interrupts Arm GIC-500 r1p1-00rel0 https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/GIC-500-Interrupt-Controller https://drive.google.com/file/d/1zhCQ6BNL8BkCSVjUEl0qtJbCJQIKdm3c/view?usp=share_link https://developer.arm.com/documentation/ddi0516/e
apu neon Arm     https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/NEON-Pipeline https://drive.google.com/file/d/15PlvTzBuECvnNJjs9jJEb5UzDEajQlBE/view?usp=share_link https://developer.arm.com/documentation/100095/0003/Advanced-SIMD-and-Floating-point?lang=en
bbram       https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/Battery-Backed-RAM    
can fd Xilinx   v3.0 https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/CAN-FD-Controller    
cfu       https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/Configuration-Frame-Unit    
debug packet controller       https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/Debug-Packet-Controller    
dpc       https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/Debug-Packet-Controller    
efuse cache            
efuse controller            
gem Cadence   r1p12 https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/Gigabit-Ethernet-MAC    
gpio            
hsdp            
i2c Cadence   dcw0701 R114 f0100 final https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/I2C-Controller    
i3c            
jtag arm dap controller       https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/Arm-DAP-Controller    
jtag tap controller            
lpd dma Xilinx   ZU+ with changes, aka Xilinx ZDMA core+ https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/LPD-DMA-Controller    
ospi Cadence   DNV3100 R003 F004 https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/Octal-SPI-Controller    
plls       https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/PLL-Clock-Generators    
pmc aes Athena   ro-2017-12-12      
pmc clkmon       https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/Clock-Monitor    
pmc dma            
pmc iro clk       https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/PMC-Source-Clocks    
pmc rsa       https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/RSA/ECDSA    
pmc rsa/ecdsa IP Cores   SX-409603203 r2.0 12 20 2016      
pmc rtc       https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/Real-Time-Clock    
pmc sbi       https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/SBI-for-JTAG-and-SelectMAP    
pmc sha3            
pmc sysmon            
pmc trng IP Cores   MP32 core r1.S https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/True-Random-Number-Generator    
ppu       https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/Platform-Processing-Unit    
ps debug Arm SoC-400 r3p2-00rel1 https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/CoreSight-Architecture https://drive.google.com/file/d/1-8TmHDcgUGIuIUpFRIOfmCUah2OjMeOh/view?usp=share_link https://developer.arm.com/documentation/ddi0480/g/?lang=en
ps ela Arm ELA-400 r2p2-00rel0   https://drive.google.com/file/d/1-8qNe9HqGS1TpMN20Cu1Z9FGGl7DQDkL/view?usp=share_link https://developer.arm.com/documentation/100127/0202/?lang=en
ps ela kit Arm LAK-500 A/I r1p0-00rel0      
ps interconnect Arm NIC-400 r0p2 https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/PS-Interconnect https://drive.google.com/file/d/1zlmp9ZIHuiLgM4jmtsm6KFZ6n2LIi1v2/view?usp=share_link https://developer.arm.com/Processors/CoreLink%20NIC-400
ps trace Arm   r0p1-00rel1   https://drive.google.com/file/d/1-6DaSAmK3Bm2p3LmWEfBa_A_4BsisQ-T/view?usp=share_link https://developer.arm.com/documentation/ddi0528/b/?lang=en
qspi     Same as MPSoC with DMA addition https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/Quad-SPI-Controller    
rpu Arm AT570 r1p3-00rel0 https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/Real-time-Processing-Unit https://drive.google.com/file/d/15R2dAtk9qytyxpOVld4UPhBltReM9tFD/view?usp=share_link https://developer.arm.com/documentation/ddi0460/d/FPU-Programmers-Model?lang=en
rpu interrupts Arm PL390 r0p0-00rel2 https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/PS-LPD-Functional-Units https://drive.google.com/file/d/1zjHLr1PnxEhnWr29_Up544eG84kZgAGj/view?usp=share_link https://developer.arm.com/documentation/ddi0416/b
scntr Arm   1.0 https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/System-Timestamp-Counter   https://developer.arm.com/documentation/102379/0100/System-Counter?lang=en
sdio Arasan   1p48 140929 https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/SD-v4.51-Controller    
smmu tbu Arm SMMU-500 r2p1 https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/Features?tocId=aZIg9~FKoe9iqKr~B6XYww https://drive.google.com/file/d/15frkOHkd1JUPkf2RsZb71lV-J9q1dDbx/view?usp=share_link https://developer.arm.com/documentation/ddi0517/d/?lang=en
smmu Arm SMMU-500 r2p4 https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/System-Memory-Virtualization-Using-SMMU-Address-Translation https://drive.google.com/file/d/15WI6AbBlP6_Zk-gd3dZrLZNNuCTAffbm/view?usp=share_link https://developer.arm.com/documentation/ddi0517/f/?lang=en
spi Cadence   r112 https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/SPI-Controller    
swdt Xilinx   0.08 https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/System-Watchdog-Timers    
ttc Cadence   T-CS- PE-000S-100 https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/Triple-Timer-Counters    
uart Arm   r1p5-00rel1 https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/UART-Controller https://drive.google.com/file/d/1-BCESIj6CxIrrN-eEH5mz6iamumtQknH/view?usp=share_link https://developer.arm.com/documentation/ddi0183/g
usb 2.0 Synopsys   USB3 3.30a core configured for USB 2.0) https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/USB-2.0-Controller    
usb 2.0 Synopsys   USB3 3.30a core configured for USB 2.0) https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/USB-2.0-Controller    
xmpu Xilinx     https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/Xilinx-Memory-Protection-Unit?tocId=lehQy03QCyRbtWedqNl9nA    
xppu Xilinx     https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/Xilinx-Peripheral-Protection-Unit?tocId=t8BYJwx1oDfMBkKh9nrINg    

Published by Google Sheets–Report Abuse–Updated automatically every 5 minutes

References