Help Debugging Embedded System, OS, and Driver Issues with 3rd-Party AMD Zynq-7000 IP

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This post lists links to AMD Zynq-7000 third-party IP details, including vendor, version, and accessible online manuals.

3rd-Party AMD Zynq-7000 IP List

This is the complete 3rd-Party AMD Zynq-7000 IP List. Vendor technical reference manuals (TRMs) have been listed if they were publically available. The table is an extension of one in the Zynq-7000 TRM titled “B.3 Module Summary” on page 784 of UG585 (v1.13) April 2, 2021. Vendor TRMs have been cached at the version used in the Zynq-7000 IP.

IP Versions Zynq-7000 to Zynq UltraScale+ MPSoC to Versal : Zynq-7000 Module Summary

Module Name	Supplier	Vendor IP Name	Vendor IP Versions	Xilinx TRM	Vendor TRM	Vendor Link
apu	Arm		r3p0	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=32	https://drive.google.com/file/d/1zWK3abNjm36euKUhkrhekHlJwerLDljM/view?usp=share_link	https://developer.arm.com/documentation/ddi0388/g/?lang=en
apu cache coherency	Arm	NIC-301	r2p2	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=119	https://drive.google.com/file/d/1zT_aXAeveFq0jcMBkm8Jg3cghYyV1jcz/view?usp=share_link	https://developer.arm.com/documentation/ddi0397/h/?lang=en
axi_hp0	Xilinx			https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=129
axi_hp1	Xilinx			https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=129
axi_hp2	Xilinx			https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=129
axi_hp3	Xilinx			https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=129
can0	Xilinx		2.0	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=554
can1	Xilinx		2.0	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=554
ddrc	Virage Logic/Synopsys		A07	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=292
debug_cpu_cti 0	Arm			https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=718	https://drive.google.com/file/d/1-UALy2JQZPjUaYcZY9Ed1h2W5vOLl2Fx/view?usp=share_link	https://developer.arm.com/documentation/ddi0314/h/Embedded-Cross-Trigger
debug_cpu_cti 1	Arm			https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=718	https://drive.google.com/file/d/1-UALy2JQZPjUaYcZY9Ed1h2W5vOLl2Fx/view?usp=share_link	https://developer.arm.com/documentation/ddi0314/h/Embedded-Cross-Trigger
debug_cpu_p mu0	Arm			https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=91	https://drive.google.com/file/d/1-UALy2JQZPjUaYcZY9Ed1h2W5vOLl2Fx/view?usp=share_link	https://developer.arm.com/documentation/ihi0091/ab
debug_cpu_p mu1	Arm			https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=91	https://drive.google.com/file/d/1-UALy2JQZPjUaYcZY9Ed1h2W5vOLl2Fx/view?usp=share_link	https://developer.arm.com/documentation/ihi0091/ab
debug_cpu_pt m0	Arm	PTM-A9	r0p0 or r1p1?	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=718	https://drive.google.com/file/d/1-UALy2JQZPjUaYcZY9Ed1h2W5vOLl2Fx/view?usp=share_link	https://developer.arm.com/documentation/ddi0401/c/introduction/about-the-ptm
debug_cpu_pt m1	Arm	PTM-A9	r0p0 or r1p1?	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=718	https://drive.google.com/file/d/1-UALy2JQZPjUaYcZY9Ed1h2W5vOLl2Fx/view?usp=share_link	https://developer.arm.com/documentation/ddi0401/c/introduction/about-the-ptm
debug_cti_etb	Arm			https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=718	https://drive.google.com/file/d/1-UALy2JQZPjUaYcZY9Ed1h2W5vOLl2Fx/view?usp=share_link	https://developer.arm.com/documentation/ddi0314/h/Embedded-Cross-Trigger
debug_cti _tpiu	Arm			https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=718	https://drive.google.com/file/d/1-UALy2JQZPjUaYcZY9Ed1h2W5vOLl2Fx/view?usp=share_link	https://developer.arm.com/documentation/ddi0314/h/Embedded-Cross-Trigger
debug_cti_ftm	Arm			https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=718	https://drive.google.com/file/d/1-UALy2JQZPjUaYcZY9Ed1h2W5vOLl2Fx/view?usp=share_link	https://developer.arm.com/documentation/ddi0314/h/Embedded-Cross-Trigger
debug_dap_ro m	Arm			https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=720	https://drive.google.com/file/d/1-UALy2JQZPjUaYcZY9Ed1h2W5vOLl2Fx/view?usp=share_link	https://developer.arm.com/documentation/ddi0314/h/Debug-Access-Port
debug_etb	Arm			https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=724	https://drive.google.com/file/d/1-UALy2JQZPjUaYcZY9Ed1h2W5vOLl2Fx/view?usp=share_link	https://developer.arm.com/documentation/ddi0314/h/Embedded-Trace-Buffer
debug_ftm	Arm			https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=657	https://drive.google.com/file/d/1-UALy2JQZPjUaYcZY9Ed1h2W5vOLl2Fx/view?usp=share_link	https://developer.arm.com/documentation/ddi0314/h/CoreSight-Trace-Sources/AMBA-AHB-Trace-Macrocell
debug_funnel	Arm			https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=723	https://drive.google.com/file/d/1-UALy2JQZPjUaYcZY9Ed1h2W5vOLl2Fx/view?usp=share_link	https://developer.arm.com/documentation/ddi0314/h/CoreSight-Trace-Funnel
debug_itm	Arm			https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=723	https://drive.google.com/file/d/1-UALy2JQZPjUaYcZY9Ed1h2W5vOLl2Fx/view?usp=share_link	https://developer.arm.com/documentation/ddi0314/h/CoreSight-Trace-Sources/Embedded-Trace-Macrocells
debug_tpiu	Arm			https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=724	https://drive.google.com/file/d/1-UALy2JQZPjUaYcZY9Ed1h2W5vOLl2Fx/view?usp=share_link	https://developer.arm.com/documentation/ddi0314/h/Trace-Port-Interface-Unit
devcfg	Xilinx?			https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=159
dmac0_ns	Arm	PL330 (DMA-330)	r1p1	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=252	https://drive.google.com/file/d/1zQAJwkxU726MSp-Hotpq8LMBVRXKwD_O/view?usp=share_link	https://developer.arm.com/documentation/ddi0424/c/?lang=en
dmac0_s	Arm	PL330 (DMA-330)	r1p1	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=252	https://drive.google.com/file/d/1zQAJwkxU726MSp-Hotpq8LMBVRXKwD_O/view?usp=share_link	https://developer.arm.com/documentation/ddi0424/c/?lang=en
gem0	Cadence		r1p23	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=485
gem1	Cadence		r1p23	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=485
gpio	Xilinx?			https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=387
gpv_qos301_cpu	Arm	QoS-301	r0p1	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=128	https://drive.google.com/file/d/1-Le6Fq07ySJH_naRUT7xVSVMi4W430k8/view?usp=share_link	https://developer.arm.com/documentation/ddi0451/b/BABFCEFF
gpv_qos301_dmac	Arm	QoS-301	r0p1	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=128	https://drive.google.com/file/d/1-Le6Fq07ySJH_naRUT7xVSVMi4W430k8/view?usp=share_link	https://developer.arm.com/documentation/ddi0451/b/BABFCEFF
gpv_qos301_iou	Arm	QoS-301	r0p1	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=128	https://drive.google.com/file/d/1-Le6Fq07ySJH_naRUT7xVSVMi4W430k8/view?usp=share_link	https://developer.arm.com/documentation/ddi0451/b/BABFCEFF
gpv_trustzone	Arm	NIC-301	#N/A	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=119	https://drive.google.com/file/d/1zT_aXAeveFq0jcMBkm8Jg3cghYyV1jcz/view?usp=share_link	https://developer.arm.com/documentation/ddi0397/h/?lang=en
i2c0	Cadence		r1p10	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=601
i2c1	Cadence		r1p10	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=601
l2cache	Arm	L2C-310 (PL310)	r3p2	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=93	https://drive.google.com/file/d/1z05GRZxHNeb9Sxrb2GgpgGLX_GKFZNxs/view?usp=sharing	https://developer.arm.com/documentation/ddi0246/f/?lang=en
mpcore	Arm	PL390	r0p0	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=227	https://drive.google.com/file/d/1zDMgWgLvmbm9JQy__2b2DroCUFzPpD0n/view?usp=share_link	https://developer.arm.com/documentation/ddi0416/b
ocm	Xilinx			https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=732
qspi	Xilinx	lqspi		https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=343
sd0	Arasan		8.9A_apr02nd_2010	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=368
sd1	Arasan		8.9A_apr02nd_2010	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=368
slcr	Xilinx	Zynq SLCR		https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=300	https://drive.google.com/file/d/1zWK3abNjm36euKUhkrhekHlJwerLDljM/view?usp=share_link	https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/system-control-register
smcc	Arm	PL353 (PL350 Series)	r2p1	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=332	https://drive.google.com/file/d/1zPBYfSvp9etK41ur_YnCeDrIIDrURys_/view?usp=share_link	https://developer.arm.com/documentation/ddi0380/g/
spi0	Cadence		r1p06	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=529
spi1	Cadence		r1p06	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=529
swdt	Cadence		Rev 07	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=242
ttc0	Cadence		Rev 06	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=246
ttc1	Cadence		Rev 06	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=246
uart0	Cadence		r1p08	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=580
uart1	Cadence		r1p08	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=580
usb0	Synopsys		2.20a	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=397
usb1	Synopsys		2.20a	https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM#page=397

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References

Zynq-7000 SoC Technical Reference Manual (UG5850) https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM [cached @ v1.13 “Third-Party IP and Standards Documents” @ page 779]
47921 - Zynq-7000 SoC - Processing System IP and Related Industry Standards https://support.xilinx.com/s/article/47921?language=en_US [cached on 2021-09-23]
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