FSBL Creation and Source Debug in Xilinx Vitis 2019.2

Xilinx_logo_1

This post demonstrates how to create and debug a ZCU102 FSBL and FSBL BSP using Xilinx’s 2019.2 Vitis, previously known as the Xilinx SDK.

Create an FSBL

#1 Run Vitis IDE 2019.2

#2 Set Workspace: to /home/demo/demobspdebug and click Launch

#3 Click the x to close the Welcome screen:

Close_welcome_screen_2

#4 Create an Application Project…

Create_application_project_3

#5 Use debugfsblbsp for Project name: , accept defaults, and click Next >

Name_project_debugfsblbsp_4

#6 Click on the Create a new platform from hardware (XSA), select zcu102, click Next >

Select_zcu102_5

#7 Click Next >

Click_next_6

#8 Select Zynq MP FSBL and click Finish

Select_zynq_mp_fsbl_7

Note: we have two FSBLs:

What we’re working on:

/home/demo/demobspdebug/debugfsblbsp/src

Part of the “platform” which we don’t use:

/home/demo/demobspdebug/zcu102/zynqmp_fsbl

#9 Build the FSBL “app” and BSP. Click on debugfsblbsp_system [zcu102] and click the hammer icon to build

Click_hammer_to_build_8

Note: High-level progress is listed in the bottom left corner of the GUI:

High_level_progress_9

Note 2:

You can switch between consoles here:

Switch_consoles_10

CDT Global Build Console

Contains all the build output

Output from this post: https://drive.google.com/file/d/1WnPVOeIhAaxuCrj3brqT8edOs-mjoedL/view?usp=sharing

Platform Tcl Console

Contains the TCL commands used to create the platform(s)

Output from this post: https://drive.google.com/file/d/1WqDV2ScxiYO3Xl6wfav4vJCh1ni3LBQ9/view?usp=sharing

Build Console [debugfsblbsp_system, Debug]

Contains “system” level commands, in this case the command that creates a BOOT.BIN using a BIF

Output from this post: https://drive.google.com/file/d/1WqOUhMh3pG2m1p0hdJJ5rUBMFNqZZZJz/view?usp=sharing

Build Console [debugfsblbsp, Debug]

Contains the build output from the FSBL we’re building (not the one under zcu102)

Output from this post: https://drive.google.com/file/d/1WsBNmWF0FhChRt_xszzC6VxOKyfriwk4/view?usp=sharing

Build Console [zcu102]

Contains the build output from the BSP build.

Output from the post: https://drive.google.com/file/d/1X-qXkF3p3iY45H90CGmLKs-3avCMHXrB/view?usp=sharing

Debug the Created FSBL

#1 Test. Right-click on debugfsblbsp, hover over Debug As, and click Launch on Hardware (System Project Debug)

System_project_debug_11

You should see:

You_should_see_12

#2 Update the debug configuration to point to the FSBL we’re working on. Click the down arrow by the bug icon and select Debug Configurations…

Debug_configuration_13

#3 Expand System Project Debug, click on SystemDebugger_debugfsblbsp_system, click on Target Setup, deselect Run psu_init, and deselect Use FSBL flow for initialization.

Set_debug_settings_14

#4 Click Apply and click Debug

Apply_and_debug_15

Note: changing the Target Setup is needed because running the FSBL twice, runs the psu_init twice, which causes problems. psu_init is a bunch of generated code that actually “connects” the Vivado output to the embedded platform output.

You should see the FSBL we’re debugging downloaded:

FSBL_debugging_download_16

#5 Look at the console output. Type:

screen /dev/ttyUSB0 115200

Note:

Ctrl-a d to detach screen -r to reattach:

You should see:

Xilinx Zynq MP First Stage Boot Loader
Release 2019.2   Dec  3 2021  - 15:41:27
PMU-FW is not running, certain applications may not be supported.

#6

(A) Click Design, (B) click xfsbl_main.c, (C) Add a “My” to the string, (D) click build, and (E) click debug

Set_debug_17

You should see the following on your terminal:

My Xilinx Zynq MP First Stage Boot Loader 
Release 2019.2   Dec  3 2021  - 16:46:24
PMU-FW is not running, certain applications may not be supported.

Enable FSBL Debug Symbols (and Fix Error)

#1 Enable debug symbols in the FSBL.

(A) Click Design, (B) right-click on debugfsblbsp [standalone on psu_cortexa53_0], (C) click C/C++ Build Settings

Enable_FSBL_debug_symbols_18

#2 Click C/C++ Build > Settings and click Miscellaneous

Build_settings_misc_19

#3 Change:

-Os -flto -ffat-lto-objects

to

-O1

…and click Apply

…and click Apply and Close

Change_misc_settings_20

You’ll see errors:

See_errors_21

Console output from this post: https://drive.google.com/file/d/1XAjRiuaPisCuMg9tSzaRu66mgRulBLzj/view?usp=sharing

#4 Fix errors. (A) Open xfsbl_config.h and…

Open_xfsbl_config.h_22

(B) set all of these from:

#define FSBL_NAND_EXCLUDE_VAL                             (0U)
#define FSBL_QSPI_EXCLUDE_VAL                             (0U)
#define FSBL_SD_EXCLUDE_VAL                               (0U)
#define FSBL_SECURE_EXCLUDE_VAL                           (0U)
#define FSBL_BS_EXCLUDE_VAL                               (0U)
#define FSBL_EARLY_HANDOFF_EXCLUDE_VAL                    (1U)
#define FSBL_WDT_EXCLUDE_VAL                              (0U)
#define FSBL_PERF_EXCLUDE_VAL                             (1U)
#define FSBL_A53_TCM_ECC_EXCLUDE_VAL                      (1U)
#define FSBL_PL_CLEAR_EXCLUDE_VAL                         (1U)
#define FSBL_USB_EXCLUDE_VAL                              (1U)
#define FSBL_PROT_BYPASS_EXCLUDE_VAL                      (1U)
#define FSBL_PARTITION_LOAD_EXCLUDE_VAL                   (0U)
#define FSBL_FORCE_ENC_EXCLUDE_VAL                        (0U)
#define FSBL_DDR_SR_EXCLUDE_VAL                           (1U)

…to (all 1U):

#define FSBL_NAND_EXCLUDE_VAL                             (1U)
#define FSBL_QSPI_EXCLUDE_VAL                             (1U)
#define FSBL_SD_EXCLUDE_VAL                               (1U)
#define FSBL_SECURE_EXCLUDE_VAL                           (1U)
#define FSBL_BS_EXCLUDE_VAL                               (1U)
#define FSBL_EARLY_HANDOFF_EXCLUDE_VAL                    (1U)
#define FSBL_WDT_EXCLUDE_VAL                              (1U)
#define FSBL_PERF_EXCLUDE_VAL                             (1U)
#define FSBL_A53_TCM_ECC_EXCLUDE_VAL                      (1U)
#define FSBL_PL_CLEAR_EXCLUDE_VAL                         (1U)
#define FSBL_USB_EXCLUDE_VAL                              (1U)
#define FSBL_PROT_BYPASS_EXCLUDE_VAL                      (1U)
#define FSBL_PARTITION_LOAD_EXCLUDE_VAL                   (1U)
#define FSBL_FORCE_ENC_EXCLUDE_VAL                        (1U)
#define FSBL_DDR_SR_EXCLUDE_VAL                           (1U)

#5 Click Save All and click Build

Save_all_and_build_23

You should see:

Expected_console_output_24

#6 Click Debug

Click_debug_25

You should see source-level debug working:

Source_level_debug_26

Enable Debug Symbols in the FSBL's BSP

#1 Enable symbols in the BSP

(A) Click Design

(B) Find and double-click the BSP’s Makefile

(C) Scroll over the editor

(D) Find:

-Os -flto -ffat-lto-objects

Enable_debug_symbols_27

#2

(A) Change:

-Os -flto -ffat-lto-objects

…to

-O1

(B) Click Save All

(C) Click Build

![Change_-Os_to_-O128](/help/fsbl-creation-and-source-debug-in-xilinx-vitis-2019-2/Change-Os_to_-O1_28.png)

You should see the correct flags in the BSP Build Console

See_correct_flags_build_code_29

Console output from this post: https://drive.google.com/file/d/1XGBCsNNTmT9hi8VAV9sA-sOwiWbUWvDT/view?usp=sharing

#3 Rebuild the FSBL

(A) Click debugfsblbsp [standalone on psu_cortexa53_0]

(B) Click Build

Rebuild_FSBL_30

You should see:

See_correct_console_output_31

Console output from this post: https://drive.google.com/file/d/1XI7fGFNiOQ6WR4WNfO1Ys-uLe94lYIX1/view?usp=sharing

(A) Open xfsbl_ddr_init.c

(B) Go to 6627:

ConfigIic = XIicPs_LookupConfig(XPAR_PSU_I2C_1_DEVICE_ID);

(C) Double-click to set a breakpoint

(D) Click debug

(E) When it hits:

               while (FsblStage<=XFSBL_STAGE_DEFAULT) {

…click Resume

Click_resume_32

(F) When it hits:

               Status = XFsbl_IicReadSpdEeprom(SpdData);

…click Step Into

Step_into_33

You should see the source code inside the BSP:

See_source_code_BSP_34

References