VHDL to Gates and Routing on an FPGA with Vivado

xilinx_logo_1

This post shows how to examine the gates and routing used to implement a VHDL design and set of constraints on the Zynq-7000 of a ZC706.

This post picks up right after [link]

Steps

Step 1: Examine the source for functionality

A) Click PROJECT MANAGER

B) Expand Design Sources (1)

C) Double-click buttonled(Behavioral) (buttonled.vhd)

D) Click on buttonled.vhd

D) Examine source

examine_source_2

Here is the source in text:

Port ( GPIO_SW_LEFT : in STD_LOGIC; GPIO_SW_CENTER : in STD_LOGIC; GPIO_SW_RIGHT : in STD_LOGIC; GPIO_LED_LEFT : out STD_LOGIC; GPIO_LED_CENTER : out STD_LOGIC; GPIO_LED_RIGHT : out STD_LOGIC);

end buttonled;

architecture Behavioral of buttonled is

begin GPIO_LED_LEFT <= GPIO_SW_LEFT; GPIO_LED_CENTER <= GPIO_SW_CENTER; GPIO_LED_RIGHT <= GPIO_SW_RIGHT; end Behavioral;

Step 2: Examine the constraints for pin and drive strength assignments

A) Expand Constraints (1)

B) Expand constrs_1 (1)

C) Double-click constrints0.xdc (target)

D) Examine constraints

examine_constraints_3

Here are the constraints in text:

set_property PACKAGE_PIN G2 [get_ports GPIO_LED_CENTER] set_property PACKAGE_PIN Y21 [get_ports GPIO_LED_LEFT] set_property PACKAGE_PIN W21 [get_ports GPIO_LED_RIGHT] set_property PACKAGE_PIN K15 [get_ports GPIO_SW_CENTER] set_property PACKAGE_PIN AK25 [get_ports GPIO_SW_LEFT] set_property PACKAGE_PIN R27 [get_ports GPIO_SW_RIGHT] set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_CENTER] set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_LEFT] set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_RIGHT] set_property IOSTANDARD LVCMOS15 [get_ports GPIO_SW_CENTER] set_property IOSTANDARD LVCMOS25 [get_ports GPIO_SW_LEFT] set_property IOSTANDARD LVCMOS25 [get_ports GPIO_SW_RIGHT]

Step 3: Examine the schematic and device view for the entire buttonled.vhd circuit

A) Click on buttonled.vhd

click_buttonled_vhd_4

B) Expand RTL ANALYSIS

C) Expand Open Elaborated Design

D) Click Schematic

E) Click on the white space above the schematic

click_on_white_space_5

Step 4: Examine the Device view while in RTL ANALYSIS

A) Ensure you did Step 3 (make sure you clicked on the white space in the schematic view)

B) Click Window

C) Click Device

click_device_6

D) Click the Float icon

click_float_icon_7

E) Place the Device window on a new screen

F) Click Auto-fit Selection so there’s a box around it

G) Click Routing Resources so there’s a box around it

H) Click Maximize

maximize_window_8

Now when you click on an element in the schematic, the Device window will automatically zoom there.

I) Click GPIO_SW_CENTER in the schematic

click_gipo_sw_center_9

You should see the Device view jump to:

device_view_switch_10

Note: this is the pad on K15 that GPIO_SW_CENTER maps to.

J) Click on the connection between GPIO_SW_CENTER and the I port of GPIO_SW_CENTER_IBUF_inst

click_connection_11

You should see the Device view jump to:

device_view_switch_12

(K1) Click and drag (K2) to zoom in

click_drag_k2_13

You should see:

k15_connection_switch_14

Notice the connection pointed at by the green arrow.

Here is the rest of the circuit in the RTL ANALYSIS view:

GPIO_SW_CENTER_IBUF_inst:

gpio_sw_center_ibuf_inst_15

k15_display_16

The connection between the O of GPIO_SW_CENTER_IBUF_inst and the I of GPIO_LED_CENTER_OBUF_inst:

i_and_o_connection_17

i_and_o_display_connection_18

Zoomed in at Start:

zoom_in_on_start_19

Zoomed in at the End:

zoom_in_on_end_20

GPIO_LED_CENTER_OBUF_inst

gpio_led_center_obuf_inst_21

gpio_led_center_obuf_inst_display_22

The connection between the O of GPIO_LED_CENTER_OBUF_inst and GPIO_LED_CENTER:

center_obuf_and_center_connection_23

center_obuf_and_center_connection_display_24

…and GPIO_LED_CENTER:

gpio_led_center_25

gpio_led_center_display_26

Step 5: Examine the Device view while in IMPLEMENTATION

Note: you will see all the routing in this view

A) Click IMPLEMENTATION

clickl_implementation_27

B) Click Window

C) Click Device

click_device_28

D) Click Float

click_float_29

E) Place the Device window on a new screen

F) Click Auto-fit Selection so there’s a box around it

G) Click Routing Resources so there’s a box around it

H) Click Maximize

click_maximize_30

You should see:

maximized_window_31

Here is the actual routing:

routing_32

ilogic_x1y340_33

board_overveiw_1_34

overveiw_switchbox_rioi_inter_35

overveiw_center_inter_r_36

larger_overveiw_37

switchbox_center_inter_l_38

travel_down_39

…then travel down:

continue_traveling_down_40

…to the end:

the_end_41

switchbox_center_inter_l_42

switchbox_center_inter_r_43

switchbox_center_inter_r_44

board_path_45

switchbox_rioi_inter_46

board_path_47

ologic_xiy236_48

…and finaly

final_result_49

Reference