Why do I need to run “Create HDL Wrapper…”

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This post lists why a Vivado IP integrator a block diagram must be wrapped in an HDL wrapper, short answer: “because a BD (block design) cannot be synthesized directly.”

In Vivado IP integrator a block diagram must be wrapped in an HDL wrapper.

Why?

From Designing IP Subsystems Using IP Integrator on p149 Xilinx provides this answer:

“The top-level HDL wrapper around the block design is needed because a BD (block design) source cannot be synthesized directly.”

Supporting Documentation

UG994 p.83

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UG994 p.84

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UG994 p.149

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UG994 p.149

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References