XCVU9P-L2FLGA2104E Decode and Its Features

This post lists a XCVU9P-L2FLGA2104E decode and its features. This part is used on the AMD Virtex UltraScale+ FPGA VCU118 Evaluation Kit @ vcu118.

XCVU9P-L2FLGA2104E Decode and Its Features

XC V U 9 P -L2 F L G A 2104 E

Code Description
XC Commercial Grade
V Virtex
U UltraScale
9 Value Index
P UltraScale+
-L2 Low Power
F Flip-Chip (1.0 mm)
L Lid SSI
G RoHS 6/6 w/ Exemption 15
A Package Designator
2104 Package Pin Count
E Extended (Tj = 0 °C to +110 °C)

Virtex UltraScale+ FPGA Feature Summary

Specification VU9P
System Logic Cells 2,586,150
CLB Flip-Flops 2,364,480
CLB LUTs 182,240
Max. Distributed RAM (Mb) 36.1
Block RAM Blocks 2,160
Block RAM (Mb) 75.9
UltraRAM Blocks 960
UltraRAM (Mb) 270
HBM DRAM (GB) –
CMTs (1 MMCM and 2 PLLs) 30
Max. HP I/O(1) 832
Max. HD I/O(2) 0
DSP Slices 6,840
System Monitor 3
GTY Transceivers 32.75 Gb/s(3) 120
GTM Transceivers 58.0 Gb/s 0
100G / 50G KP4 FEC 0
Transceiver Fractional PLLs 60
PCIE4 (PCIe Gen3 x16)(4) 6
PCIE4C (PCIe Gen3 x16 / Gen4 x8)(4)(5) 0
150G Interlaken 9
100G Ethernet w/RS-FEC 9

Footnotes

  1. HP = High-performance I/O with support for I/O voltage from 1.0V to 1.8V.
  2. HD = High-density I/O with support for I/O voltage from 1.2V to 3.3V.
  3. GTY transceivers in the FLGF1924 package support data rates up to 16.3 Gb/s. See Table 14.
  4. Supported PCIe configurations are determined by transceiver count.
  5. This block operates in compatibility mode for 16.0 GT/s (Gen4) operation. Go to PG213, UltraScale+ Devices Integrated Block for PCI Express Product Guide, for details on compatibility mode.

Virtex UltraScale+ Device-Package Combinations and Maximum I/Os

Package (1)(2)(3)(4)(5) Package Dimensions (mm) VU9P
    HP, GTY
FLGA2104 47.5 x 47.5 832, 52
FLGB2104 47.5 x 47.5 702, 76
FLGC2104 47.5 x 47.5 416, 104
FSGD2104 47.5 x 47.5 676, 76
FLGA2577 52.5 x 52.5 448, 120

Footnotes

  1. Package code definitions may vary by device family.
  2. Dimensions are nominal, in millimeters.
  3. See Xilinx/AMD packaging documentation for tolerances.
  4. Pin counts and I/O assignments depend on package type.
  5. Additional restrictions may apply for GTY/HP interfaces.

Original Tables