Add an embeddedsw Driver to a 2019.1 BSP From the Command Line

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This post demonstrates how you can manually add an embeddedsw driver to an XSDK FSBL BSP.

Steps

XP=~/xsdk/SDK/2019.1

WS=~/plxprjs/testfsbl

HD=~/plxprjs/xilinx-zcu102-2019.1/project-spec/hw-description/system.hdf

# Create the workspace directory

mkdir -p $WS

# Create HW from the HDF

$XP/bin/xsct -eval “setws $WS; createhw -name hw0 -hwspec $HD”

# Create the FSBL

$XP/bin/xsct -eval “setws $WS; createapp -name fsbl -app {Zynq MP FSBL} -proc psu_cortexa53_0 -hwproject hw0 -os standalone”

# Build the FSBL

$XP/bin/xsct -eval “setws $WS; projects -build”

# Copy the driver into the right directory

cp -R $XP/data/embeddedsw/XilinxProcessorIPLib/drivers/spi_v4_4 $WS/fsbl_bsp/psu_cortexa53_0/libsrc/

# Build it (you’ll see errors)

$XP/bin/xsct -eval “setws $WS; projects -build”

# Why does this work?

cat $WS/fsbl_bsp/Makefile

# BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile)

This line ^^^^ simply includes Makefiles that are in the _right_ location

Note

You will need to manually set defines for your build. For this example:

# XPAR_XSPI_NUM_INSTANCES

# XPAR_SPI_0_DEVICE_ID

# XPAR_SPI_0_BASEADDR

# XPAR_SPI_0_FIFO_EXIST

# XPAR_SPI_0_SLAVE_ONLY

# XPAR_SPI_0_NUM_SS_BITS

# XPAR_SPI_0_NUM_TRANSFER_BITS

# XPAR_SPI_1_DEVICE_ID

# XPAR_SPI_1_BASEADDR

# XPAR_SPI_1_FIFO_EXIST

# XPAR_SPI_1_SLAVE_ONLY

# XPAR_SPI_1_NUM_SS_BITS

# XPAR_SPI_1_NUM_TRANSFER_BITS

# Example from design:

fsbl_bsp/psu_cortexa53_0/include/xparameters.h:1054:

#define XPAR_SPI_0_DEVICE_ID 0U

fsbl_bsp/psu_cortexa53_0/include/xparameters.h:1055:

#define XPAR_SPI_0_BASEADDR 0xA0000000U

fsbl_bsp/psu_cortexa53_0/include/xparameters.h:1056:

#define XPAR_SPI_0_HIGHADDR 0xA000FFFFU

fsbl_bsp/psu_cortexa53_0/include/xparameters.h:1057:

#define XPAR_SPI_0_FIFO_DEPTH 16U

fsbl_bsp/psu_cortexa53_0/include/xparameters.h:1058:

#define XPAR_SPI_0_FIFO_EXIST 1U

fsbl_bsp/psu_cortexa53_0/include/xparameters.h:1059:

#define XPAR_SPI_0_SPI_SLAVE_ONLY 0U

fsbl_bsp/psu_cortexa53_0/include/xparameters.h:1060:

#define XPAR_SPI_0_NUM_SS_BITS 1U

fsbl_bsp/psu_cortexa53_0/include/xparameters.h:1061

:#define XPAR_SPI_0_NUM_TRANSFER_BITS 8U

fsbl_bsp/psu_cortexa53_0/include/xparameters.h:1062:

#define XPAR_SPI_0_SPI_MODE 0U

fsbl_bsp/psu_cortexa53_0/include/xparameters.h:1063:

#define XPAR_SPI_0_TYPE_OF_AXI4_INTERFACE 0U

fsbl_bsp/psu_cortexa53_0/include/xparameters.h:1064:

#define XPAR_SPI_0_AXI4_BASEADDR 0U

fsbl_bsp/psu_cortexa53_0/include/xparameters.h:1065

#define XPAR_SPI_0_AXI4_HIGHADDR 0U

fsbl_bsp/psu_cortexa53_0/include/xparameters.h:1066:

#define XPAR_SPI_0_XIP_MODE 0U

fsbl_bsp/psu_cortexa53_0/include/xparameters.h:1067:

#define XPAR_SPI_0_USE_STARTUP 0U

Reference

The Xilinx graphic is from [link]