#define

Dec 4, 20213 min read

FSBL Creation and Source Debug in Xilinx Vitis 2019.2

This post demonstrates how to create and debug a ZCU102 FSBL and FSBL BSP using Xilinx's 2019.2 Vitis, previously known as the Xilinx...

Sep 11, 20211 min read

This post demonstrates how you can manually add an embeddedsw driver to an XSDK FSBL BSP. Steps XP=~/xsdk/SDK/2019.1...

Jan 1, 202110 min read

This post shows how to store LoRaWAN device-specific information on an external EEPROM for the ATSAMR34 platform. It also demonstrates...

Dec 25, 20202 min read

This post shows how to use devshell to debug the FSBL on a ZCU102 build. It also includes changes that enable source-level debug and...

Dec 10, 20201 min read

This post lists the output of aarch64-none-elf-size fsbldebug.elf |tee "fsbldebug.elf.size" for each value of FSBL code include options...

Jan 23, 20204 min read

This post describes how to boot a "Hello World" application on the Ultra96v2's R5 processor over JTAG. The Xilinx Software Commandline...