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This post lists Vivado command line options from Vivado v2023.1. demouser@fpgadev:~/Desktop$ vivado -help vivado Description: Vivado v2023.1 (64-bit) SW Build 3865809 on Sun May 7 15:04:56 MDT 2023 IP Build 3864474 on Sun May 7 20:36:21 MDT 2023 Tool Version Limit: 2023.05 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023 Syntax: vivado [-mode ] [-init] [-source ] [-nojournal] [-appjournal] [-journal ] [-nolog] [-applog] [-log ] [-version] [-tclargs ] [-tempDir ] [-robot ] [-verbose] [] Usage: Name Description -------------------------- [-mode] Invocation mode, allowed values are 'gui', 'tcl', and 'batch' Default: gui [-init] Source vivado.tcl file [-source] Source the specified Tcl file [-nojournal] Do not create a journal file [-appjournal] Open journal file in append mode [-journal] Journal file name Default: vivado.jou [-nolog] Do not create a log file [-applog] Open log file in append mode [-log] Log file name Default: vivado.log [-version] Output version information and exit [-tclargs] Arguments passed on to tcl argc argv [-tempDir] Temporary directory name. [-robot] Robot JAR file name. [-verbose] Suspend message limits during command execution [] Load the specified project (.xpr) or design checkpoint (.dcp) file Categories:

Versal has an ARM GIC-500 (Global Interrupt Controller) connected to its APU. The GIC-500 implements the ARM GICv3 standard. UltraScale+, on the other hand, has a GIC-400 connected to its APU. The GIC-400 implements the ARM GICv2 standard. If you read through the ARM GICv3 and GIC-500 documentation, there are some references to “backwards compatibility” or “legacy operation.” They describe a feature that would allow GICv2 code to run on platforms with a GICv3. This implies that interrupt code written for UltraScale+’s GIC-400/GICv2 could run unmodified on Versal. That is not the case. This article covers the limitations of backwards compatibility and where backwards compatibility does work. The GIC-500 TRM states (r1p1 section 2.3.4 / page 32): You can configure the Distributor part of the GIC-500 at build time to support limited backwards compatibility with GICv2. If this support is configured, the Distributor resets to backwards compatibility mode. The ARE setting in GICD_CTLR, which disables backwards compatibility, is programmable when backwards compatibility support is configured. That section also describes a few limitations to backwards compatibility – but they’re minor limitations. Based on those limitations most US+ interrupt code should only require minor changes to work on Versal. The backwards compatibility option in GIC-500 is configurable when the silicon is built (see GIC-500 TRM r1p1 section 1.5 / page 19 – “GICv2 backwards compatibility support”). If enabled, the GIC will be in backwards compatibility mode by default after POR, and the ARE_S / ARE_NS bits in the GICD_CTLR register will both be 0 (GIC-500 TRM r1p1 page 42 “In backwards compatibility mode, where ARE = 0” and pages 43-45 (paraphrased) “The reset value of GICD_CTLR… ARE_S/NS being set means no GICv2 backwards compatibility support included.”) We can verify this on Versal. If you probe GICD_CTLR (0x00F9000000) after boot, the register value is 0x1. The ARE_S and ARE_NS bits are not set, meaning that backwards compatibility is enabled in silicon and currently active. (For comparison, if you try this on Versal QEMU, the register will read 0x30 – both ARE bits are set, meaning that backwards compatibility is not supported. This is because the QEMU implementation of GIC-500 does not support backwards compatibility.) After confirming that backwards compatibility is supported and enabled on Versal, you may try to run UltraScale+ interrupt code on Versal, and, even if you patch the code to work around the few limitations described in GIC-500 TRM section 2.3.4, you will likely find that it doesn’t work. This is because of a more major limitation in the backwards compatibility support: “You can configure the Distributor part of the GIC-500 at build time to support limited backwards compatibility with GICv2.” Only the distributor part of the GIC-500 supports backwards compatibility. This is due to the way the GIC is structured in the system. A hint is available here: https://lore.kernel.org/linux-arm-kernel/20220211235513.cplmvgfuwe3dhzbs@nearby/ No, this description is for the architecture as a whole. ARE being disabled int the GIC doesn’t mean it is disabled overall, and the CPU is free to implement the CPU interface by any mean it wants as long as it communicates with the GIC using the Stream Protocol. The GIC-500 does not implement all of GICv3. Interrupt handling is spread across two parts – the GIC itself and a CPU interface. The CPU interface is silicon that is physically located inside the A72 CPU cores. Backwards compatibility only applies to the distributor part of the GIC-500; it doesn’t affect the CPU interface. If the ARE_S/NS bits are zero, then the GICD_* registers (for the distributor in the GIC-500) will support backwards compatibility and UltraScale+ / GICv2 / GIC-400 code that uses GICD_* registers will work on Versal / GICv3 / GIC-500 (as long as you patch it for the few limitations described in GIC-500 TRM section 2.3.4). But other register blocks such as GICC_*, GICH_*, GICV_* are implemented in the CPU interface, not in the GIC-500 – in fact, you won’t even find any referenecs to GICC/GICH/GICV in the GIC-500 TRM. Backwards compatibility mode in the GIC-500 will not affect these, and any code that touches these registers will have to be updated when you migrate from UltraScale+ to Versal. References ARM GIC-500 TRM (DDI 0516E) r1p1 https://documentation-service.arm.com/static/5e9085b8c8052b1608761814 ARM GICv3 Architecture Specification (IHI 0069A) https://documentation-service.arm.com/static/6012f824773bb020e3de7aad AMD/Xilinx Versal TRM (AM011) https://docs.xilinx.com/r/en-US/am011-versal-acap-trm AMD/Xilinx UltraScale+ TRM (UG1085) https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm Header image from https://www.xilinx.com/products/silicon-devices/acap/versal-ai-core.html#video

Details on abbreviations, acronyms, and other terms. In this post, *O means that a component is optional and is not present in every Versal model. See AM011 section "Integrated Peripheral Options" for details. For high-level diagrams, refer to: AM011 figure "SoC Block Diagram" (link) AM011 section "Hardware Architecture" (link) Miscellaneous ACAP Adaptive Compute Acceleration Platform – how AMD marketing describes/classifies the Versal product Major system components Intelligent Engines Name for the DSPs and AIEs AIE AI Engine – usually refers to the default DSP-optimized version of the AI Engine AIE-ML AI Engine, ML-optimized version (for machine learning training & inference) DSP Dedicated DSP (digital signal processor) accelerator engines, located inside the PL. Adaptive Engines / Adaptable Engines Name for the FPGA and the BlockRAM/UltraRAM that it contains. Does not include the DSP blocks. PL Programmable Logic (the FPGA & its RAM). The DSP engines are located within the PL, and the AIEs connect to the PL. “PL” is also the name of a power domain, which includes the PL (FPGA/DSP), AIEs, and some peripherals. Scalar Engines Name for the ARM cores (APU + RPU) APU Application Processing Unit. On Versal, this consists of the two ARM Cortex-A72 cores. RPU Realtime Processing Unit. On Versal, this consists of the two ARM Cortex-R5F cores. OCM 256kb of ECC On-Chip Memory. This is connected directly to the RPU and indirectly to the APU. CIPS Control, Interfaces, and Processing System. This includes the Scalar Engines (APU/RPU), PMC, and CPM. Formerly called the PS on Zynq-7000 and UltraScale+. CCI Cache-Coherent Interconnect for APU L2 cache. See AM011 chapter “Cache Coherent Interconnect.” CPM, CCIX, CXL [Cache] Coherent Module with PCIe. There are two versions, CPM4 and CPM5. This is an optional feature, not all Versal models have one. The CPM4 variant has a CCIX interconnect, see AM016 for details. The CPM5 variant has a CXL interconnect which can provide cache coherency with external PCIe devices. See AM011 page 26 (in v1.5). PMC Platform Management Controller. This includes the RCU, PPU, and to an extent also the PSM – a set of processors that control boot and system monitoring & management. The PMC also includs 128kb of PMC RAM which is used by the PLM, IO peripherals, debug interfaces, registers, the system monitor, RTC, configuration interfaces, and security modules. The PMC also has its own power domain, with one exception: though the PSM is logically part of the PMC, physically the PSM is located in the LPD. See AM011 "Platform Managment Controller", which includes a block diagram of the PMC. RCU ROM Code Unit. This block contains the RCU ROM (equivalent of BootROM on the Zynq-7000 and UltraScale+), a triple-redundant MicroBlaze processor (which executes the RCU ROM), and the PUF. PPU Platform Processing Unit. This includes the PPU itself (a triple redundant MicroBlaze processor) and some dedicated PPU RAM. The PPU executes the PLM. See AM011 chapter "Platform Processing Unit" (chapter 31 / page 309 in v1.5). PSM Processing System Management controller. This executes the PSMFW. This is logically part of the PMC but is in the LPD. The PSM does power management for the PS. See AM011 chapter "Processing System Manager" (chapter 32 / page 316 in v1.5). NoC Network on Chip. This connects the PS, PL, AIEs, DDR controller, CPM, NPI, and HBM. Other system components Networking MRMAC *O 100G Multirate Ethernet MAC DCMAC *O 600G Channelized Multirate Ethernet MAC ILKN *O 600G Interlaken Core Debug ARM DAP ARM Debug Access Port. Used to perform debug operations on the APU and RPU. TAP [JTAG] Test Access Port DPC Debug Packet Controller. See AM011 section "Debug Packet Controller." SBI Supervised Boot Interface. See AM011 chapter "SBI for JTAG and SelectMAP." Security & crypto HSC *O High-Speed Crypto Engine eFUSE One-time-programmable fuses in the chip. eFuses can be blown to enable secure boot and other security options. They can also store secure boot keys. BBRAM Battery-backed RAM. This is a small (288 bit) RAM unit inside the Versal, but requires an external battery to be connected to preserve data when the chip is powered off. Can store things like encryption & authentication keys. See AM011 chapter "Battery-Backed RAM." PUF Physically Unclonable Function. This is a security unit in the PMC. See AM011 chapter "PMC Security Units." KEK Key Encryption Key - generated by the PUF. Used by certain secure boot methods. TRNG True Random Number Generator. This is a security unit in the PMC. See AM011 chapter "PMC Security Units." SSS Secure Stream Switch. This connects the two PMC DMAs, AES-GCM, SHA3-384, and SBI. See AM011 chapter "Secure Stream Switch." XMPU Xilinx Memory Protection Unit. There are multiple on the Versal. These control access to memories on the system. See AM011 section "Xilinx Memory Protection Unit." XPPU Xilinx Peripheral Protection Unit. There are multiple on the Versal. These can block access to various configuration registers. See AM011 chapter "Xilinx Peripheral Protection Unit." Configuration CFU, CFI, CRAM Configuration Frame Unit and Configuration Frame Interface, used to configure the PL. The CFU is a bridge to transfer data between the PMC main switch and into the CFI & PL Configuration RAM (CRAM). NPI NoC Programming Interface - used to configure the NoC, DDR controller, AI Engines, transceivers, and some other things in the PL and SPD. Memory XRAM *O Accelerator RAM. See AM011 section "Accelerator RAM." TCM Tightly-coupled Memory. See AM011 section "Tightly-coupled Memories" SMMU System Memory Management Unit. See AM011 section "System Memory Management Unit." Miscellaneous DNA A 128-bit device identifier. No two Versal chips have the same DNA value. See AM011 section "DNA Introduction." VDU *O Video Decoder Unit Power domains For more details on power domains, see AM011 section "Power Domains." (link) FPD Full Power Domain LPD Low Power Domain BPD Battery Power Domain SPD System Power Domain Software Configuration and Boot PDI Programmable Device Image. A file that contains configuration data needed to initialize components on the chip. See https://support.xilinx.com/s/article/1146981?language=en_US PSMFW PSM Firmware. This is loaded into and executed by the PSM during boot. PLM Platform Loader and Manager. This is roughly equivalent to the FSBL (First Stage Boot Loader) on the Zynq-7000 and UltraScale+. References AM011: Versal Adaptive SoC Technical Reference Manual UG1304: Versal Adaptive SoC System Software Developers Guide Versal chip image from https://www.xilinx.com/products/silicon-devices/acap/versal-ai-core.html#video

Introduction This article will show you how to use Vivado to read back the bitstream programmed into a physical Zynq-7000 device. The bitstream that is read back will differ from the bitstream generated by Vivado because Vivado generates a bitstream containing configuration commands, whereas the readback file contains only the configuration data. However, comparing the two files to verify that they match is possible. We have another post on the multiple bitstream data formats and how to analyze a bitstream: (coming soon). Note that the hardware will disable bitstream readback while an encrypted bitstream is programmed. Readback only works for non-encrypted bitstreams. Program the device As a prerequisite, you’ll need a Zynq-7000 with a bitstream programmed into it. You can skip this section if you already have a bitstream programmed into your device. You can generate a bitstream by following Part 1 (through step 25) of Run Hello World on a ZC702. That guide was written for Vivado 2018.2, but those steps still work in 2023.1. That will generate ps7_init.tcl and the bitstream, located at: /project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.tcl /project_1/project_1.runs/impl_1/design_1_wrapper.bit Set your board to JTAG boot mode – on a ZC702, all pins in blue SW16 should be to the side opposite the SD card / power connector / power switch. Program the bitstream into the device using xsct: /tools/Xilinx/Vitis/2023.1/bin/xsct connect source /path/to/ps7_init.tcl targets 1 # (select the APU target; run just `targets` to see the list of targets and their numbers) ps7_init ps7_post_config targets 4 # (select the FPGA target) fpga /path/to/bitstream.bit At this point, the INIT_B and DONE pins should both be high. On the ZC702 dev board, the corresponding LEDs should be green. Read back the bitstream Launch Vivado into Tcl mode. Alternatively, you can use the Tcl console from inside the Vivado GUI. Connect to your SmartLynq, or to your local hw_server instance if you are using USB-JTAG. xsct should have already launched hw_server while programming the bitstream. If not, you can launch it manually by running "/tools/Xilinx/Vitis/2023.1/bin/hw_server -s tcp::3121" /tools/Xilinx/Vivado/2023.1/bin/vivado -mode tcl open_hw_manager connect_hw_server -url localhost:3121 get_hw_targets => 10.209.202.1:3121/xilinx_tcf/Digilent/210203AB90E5A current_hw_target => 10.209.202.1:3121/xilinx_tcf/Digilent/210203AB90E5A open_hw_target get_hw_devices => arm_dap_0 xc7z020_1 current_hw_device => xc7z020_1 readback_hw_device -readback_file /path/to/readback.rbd -bin_file /path/to/readback.bin -force This will create two copies of the bitstream, one in rbd format and one in bin format. You can also read back the bitstream in other formats – see readback_hw_device -help. References UG908 – Vivado Design Suite User Guide: Programming and Debugging Section “Bitstream Verify and Readback for FPGAs and MPSoCs” (link to section) Logo from https://library.amd.com/media/ (requires a password)

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Welcome to the world of FPGA design, where your ideas can come to life in silicon! This blog post discusses common processes and tools to turn HDL into hardware. First, we'll give a quick synthesis overview - this is where your HDL code gets transformed into the actual logic on an FPGA. It's like a puzzle where your code pieces fit into the FPGA's configurable logic blocks (CLBs), Block RAMS (BRAMs), and other elements (a full list is given below). Next, we discuss the cool tools and compilers that perform synthesis from HDL (Hardware Description Language) and can help simulate designs. Lastly, we'll cover High-Level Synthesis tools that can transform C/C++/System C into HDL. It's all about choosing the right tool for the job. So, buckle up, and let's explore how to go from lines of HDL to a chip that does your bidding! HDL CLB Translation Process The process of translating HDL (Hardware Description Language) code into a configuration for the CLBs (Configurable Logic Blocks) of an FPGA (Field-Programmable Gate Array) is known as "synthesis." Here's a brief overview of the steps involved in this process: HDL Coding: The desired digital circuit is initially described using a Hardware Description Language such as VHDL or Verilog. This HDL code represents the logical behavior and structure of the digital circuit. Synthesis: The synthesis tool takes the HDL code as input and translates it into a netlist. This netlist describes the circuit in terms of generic logic gates and interconnections. During synthesis, the tool optimizes to reduce the circuit's complexity, improve performance, or meet other design constraints. Technology Mapping: The next step is to map the generic logic elements in the netlist to the specific resources available on the FPGA. For FPGAs, this involves mapping the logic to Configurable Logic Blocks (CLBs), Block RAMs (BRAMs), Digital Signal Processing (DSP), I/O Blocks (IOBs), Clock Management Tiles (CMTs), Switch Matrix or Interconnect, SerDes (Serializer/Deserializer) Blocks, Transceivers, Hard IP Cores, Embedded Processors, Configuration Memory, Power Management Blocks, and Analog-to-Digital Converters (ADCs), and now AI Engines! Place and Route: The "place and route" step is performed after technology mapping. Here, the tool assigns the mapped elements to specific elements on the FPGA and determines the interconnections' routing. Bitstream Generation: A bitstream is generated once the design is successfully placed and routed. This bitstream is a binary file containing the FPGA configuration data. When loaded into the FPGA, this bitstream configures the resources to implement the desired circuit. Loading to FPGA: Finally, the bitstream is loaded onto the FPGA, configuring it to perform the functions defined by the original HDL code. FPGA design software like Xilinx Vivado, Intel Quartus Prime, and others facilitate this process, providing integrated environments for HDL coding, synthesis, simulation, and bitstream generation. FPGA Synthesis Tools Here are some of the most widely used tools that synthesize a bitstream from a design described in HDL. AMD (Xilinx) Vivado Design Suite: This software suite for designing systems using Xilinx FPGAs. Vivado includes tools for HDL synthesis, simulation, and debugging. It supports VHDL, Verilog, and SystemVerilog. Intel Quartus Prime: Similar to Vivado, but for Intel (formerly Altera) FPGAs. Quartus Prime supports VHDL, Verilog, and SystemVerilog for design entry, synthesis, and verification. Lattice Diamond: This is the design software for Lattice Semiconductor FPGAs. It supports HDL synthesis and is used for Lattice's low-power FPGA families. Microchip Libero SoC: This tool is used for Microchip (used to be Microsemi) FPGAs. It provides HDL synthesis, simulation, and other design tools. GHDL: An open-source simulator for VHDL that can be used with other FPGA design tools. Icarus Verilog: Another open-source tool, this time for Verilog HDL. It is primarily a simulator but can be used as part of a toolchain for FPGA design. Synopsys Synplify/Synplify Pro: These synthesis tools support VHDL, Verilog, and SystemVerilog, and are often used with other FPGA design software. ModelSim and QuestaSim from Siemens: These are comprehensive simulation and debugging tools for VHDL and Verilog often used in FPGA development. HLS In addition to these tools, there are high-level synthesis (HLS) tools like AMD's Vitis HLS, which allow designers to write code in C, C++, or SystemC and then compile it into HDL for FPGA implementation. High-Level Synthesis (HLS) tools are designed to allow engineers and designers to write their algorithms in high-level programming languages like C, C++, or SystemC and then compile these into hardware description languages (HDL) for implementation on FPGAs or ASICs. Here are some notable HLS tools: AMD Vitis HLS: This tool enables designers to use C or C++ to develop their algorithms, which are then synthesized into optimized RTL code for Xilinx FPGAs. Intel FPGA SDK for OpenCL (Legacy): This tool allows developers to write their FPGA designs in OpenCL, a high-level, parallel programming language, and compile them for use on Intel FPGAs. Cadence Stratus High-Level Synthesis: Stratus HLS from Cadence allows for C/C++/SystemC-based design entry, providing an efficient path to RTL for both FPGA and ASIC implementations. Synopsys Synphony HLS: This tool from Synopsys enables synthesizing high-level Matlab and Simulink models, along with C and C++ code, into RTL for both FPGAs and ASICs. Siemens Catapult High-Level Synthesis and Verification: Catapult HLS allows for C++ and SystemC design entry and provides advanced power, performance, and area optimizations. Siemens Precision FPGA Synthesis: Precision Synthesis is an FPGA vendor-independent solution. Precision has tight integration across the Siemens FPGA flow from C++/SystemC/RTL design through simulation and formal verification to board design. Microchip's SmartHLS: Implement your design in C++ software and verify the functionality with software tests. Then, use SmartHLS high-level synthesis software to compile the C++ program into functionality-equivalent Verilog hardware modules. Mathworks HDL Coder: This tool generates Verilog, SystemVerilog, and VHDL code for FPGA and ASIC designs. These tools may significantly streamline the FPGA design process, enabling designers to work at a higher level of abstraction, possibly accelerating the development cycle. However, these gains may not materialize in practice due to the different "execution" models C/C++ and HDLs abstract.

Welcome to my latest blog post, "Mastering Remote Access: Secure GUI Solutions through SSH Tunneling." In today's increasingly remote and digital workspace, accessing a graphical user interface (GUI) on a remote computer securely is not just a convenience—it's a necessity. Whether you're a system administrator managing servers, a developer working on a remote machine, or need to access your office computer from home, the ability to interact with a remote desktop environment securely and efficiently can greatly enhance productivity and workflow. This post delves into remote GUI access, focusing on robust and secure methods utilizing SSH tunneling. From the simplicity of X11 forwarding to the comprehensive capabilities of VNC and RDP, we'll guide you through the best practices and tools to master remote GUI access securely and efficiently. Join us as we explore these technologies' ins and outs, helping you integrate them into your remote working toolkit seamlessly. Secure GUI Solutions Through SSH Tunneling Using SSH tunneling to access a GUI securely on a remote computer is a reliable and secure method. There are a few options you can consider: 1. X11 Forwarding: X11 forwarding with SSH allows you to run graphical applications on a remote machine and forward the display to your local machine. To use X11 forwarding, you need an X server on your local machine. On Linux, this is typically already present. You can use Xming or VcXsrv on Windows and macOS, XQuartz. To enable X11 forwarding, connect to the remote machine using ssh -X [username]@[host] or ssh -Y [username]@[host] (the -Y option is for trusted X11 forwarding). Once connected, you can launch GUI applications from the command line, which will be displayed on your local machine. 2. Virtual Network Computing (VNC) over SSH: VNC is a popular choice for remote desktop access. It can be made secure by tunneling it through SSH. First, set up a VNC server on the remote machine. Tools like TightVNC, TigerVNC, or RealVNC can be used. On your local machine, establish an SSH tunnel to the remote host by running ssh -L 5901:localhost:5901 -C -N -l [username] [remote_host], assuming the VNC server is running on display :1. Then, use a VNC client on your local machine to connect to localhost:5901. The VNC session will be secured through the SSH tunnel. 3. Remote Desktop Protocol (RDP) over SSH: RDP is mainly used for Windows machines but can be installed on Linux systems using xrdp. Like VNC, you can tunnel RDP sessions through SSH for added security. The process involves forwarding the appropriate port (usually 3389 for RDP) through SSH and then connecting to the local port with an RDP client. 4. NoMachine (NX) over SSH: NoMachine is a powerful and efficient remote desktop software that provides a smooth and responsive GUI experience, even over slow network connections. It can also be tunneled through SSH for secure connections. 5. Secure Web-based Solutions: Tools like Apache Guacamole provide web-based remote desktop access. It supports VNC, RDP, and SSH and can be configured to run securely over HTTPS. Each method has advantages and suitability depending on the network environment, the operating systems in use, and the level of graphical performance needed. X11 forwarding is generally good for individual applications, while VNC and RDP are better for a full desktop experience. NoMachine offers a balance between performance and ease of setup. Guacamole is ideal for accessing remote desktops from within a web browser without client software installation. Additional Secure GUI Solutions Through SSH Tunneling Here are some additional options: 6. Remote Desktop Gateway aka RD Gateway: This server is a gateway between external devices and the internal network's remote desktop servers. It uses the Remote Desktop Protocol (RDP) alongside HTTPS for secure communication. 7. TeamViewer or AnyDesk: These are commercial remote desktop applications known for their ease of use and strong security features. They are suitable for individual and enterprise use, offering encrypted, stable remote connections. 8. Parsec: Originally designed for game streaming, Parsec also offers high-performance remote desktop access. It's known for its low latency and high-quality video, making it suitable for graphics-intensive applications. 9. Chrome Remote Desktop: A simple and easy-to-use solution for remotely accessing your desktop from another machine via the Chrome browser or a Chromebook. It's secure and works across different platforms. 10. CyberArk Alero: Specifically designed for secure remote access to critical systems, it's used in enterprise environments where security is paramount. 11. Jump Desktop: A secure and reliable remote desktop application that supports RDP and VNC. It is known for its simplicity and ease of use. 12. ThinLinc: A remote desktop server solution that is particularly effective for Linux/Unix servers and clients. It uses SSH for secure communication. 13. HP Remote Graphics Software (RGS): Aimed at professionals needing high-end graphics capabilities remotely, HP RGS is a robust solution for graphic-intensive applications. Each of these additional options caters to different needs and setups. While some are more suited for individual and casual use, others are designed for enterprise environments with stringent security requirements. Your choice will depend on factors like the nature of the tasks, the required performance level, the security needs, and the ease of setup and use.

This post shows some Lawrence Berkeley National Lab 88-Inch Cyclotron Berkeley Accelerator Space Effects Facility (BASE) photos I took during two recent trips to test AMDs Versal with the Xilinx Radiation Test Consortium. Cyclotron Patent Picture of the "Method and apparatus for the acceleration of ions" patent: https://patents.google.com/patent/US1948384A/en Cave One of the "Caves" Where the Versal Was Exposed to the Beam Cyclotron Accelerator Room 88-Inch Cyclotron RF Inside the Cyclotron Accelerator Cyclotron Control Room Inside the "Love Shack" aka the Control Room Cyclotron Beam Control Panel Cyclotron Beamline Attenuator Control Chassis More Info See https://cyclotron.lbl.gov/ for more information.

This post answers, "How do I configure Linux Linux for Non-ARP UDP Communication with an Embedded Target?" Introduction Learn to configure a Linux system to connect with an embedded target that lacks ARP over UDP support. This guide simplifies the process for seamless communication. Prerequisites Linux system access with 'sudo' privileges. Configuration Overview Target IP: 172.16.30.1, MAC: 5e:ea:50:05:1a:b5 Host IP: 172.16.30.2, MAC: 5e:e0:06:50:05:ee Quick Setup Steps Hardware Connection Connect the Linux host and embedded target using an Ethernet cable. Power On Activate the embedded target. Identify [interface] Open terminal, run ifconfig, and note the Ethernet interface (e.g., ens33). Configure MAC Address Disable interface: sudo ifconfig [interface] down Set MAC address: sudo ifconfig [interface] hw ether 5e:e0:06:50:05:ee Enable interface: sudo ifconfig [interface] up Assign IP Address: Assign IP via terminal: sudo ifconfig [interface] 172.16.30.2 netmask 255.255.255.0 Update ARP Table: Add static ARP entry: sudo arp -i [interface] -s 172.16.30.1 5e:ea:50:05:1a:b5 Verify Configuration Check ARP mapping with arp -a. Conclusion With these steps, your Linux system will be ready to interface with an embedded target that doesn't support ARP over UDP, ensuring smooth communication and operation. Additional Info On ARP The ARP table facilitates the translation between IP addresses and MAC addresses for local network communication. The table is accessed whenever a device needs to establish a direct communication link with another device on the same local network. References Tux from [link]

This post shows you how to find the MD5 SUM of a file on Windows 10 Pro. Steps to Find the MD5 SUM of a File on Windows Step 1: Open PowerShell Press: Windows Key + r, Type: powershell Step 2: Type: Get-FileHash "D:\installers\amd\2023.2\FPGAs_AdaptiveSoCs_Unified_2023.2_1013_2256.tar.gz" -Algorithm MD5 Example Output: Algorithm Hash Path --------- ---- ---- MD5 64D64E9B937B6FD5E98B41811C74AAB2 D:\installe... Reference Windows Version: From PowerShell or CMD, run: PS C:\Users\Zach Pfeffer> systeminfo | findstr /B /C:"OS Name" /B /C:"OS Version" Output: OS Name: Microsoft Windows 10 Pro OS Version: 10.0.19045 N/A Build 19045 Windows 10 Logo: https://commons.wikimedia.org/wiki/File:Windows_logo_-_2012_%28dark_blue%29.svg

This post is a Logitech M720 at-a-glance. It includes links to get support. M720 At-A-Glance Buttons Point and Scroll Logitech M720 Triathlon Product Overview https://www.logitech.com/en-us/products/mice/m720-triathlon.910-004790.html Software Downloads Windows 10 Logi: Options+, Firmware Update Tools, and Logitech Options Downloads https://support.logi.com/hc/en-us/articles/360024698414--Downloads-M720-Triathlon-Multi-Device-Mouse Specs & Details Dimensions Mouse Height: 4.53 in (115 mm) Width: 2.91 in (74 mm) Depth: 1.78 in (45 mm) Weight (with batteries): 4.76 oz (135 g), with AA battery Logitech Unifying receiver Height: 0.74 in (18.7 mm) Width: 0.57 in (14.4 mm) Depth: 0.24 in (6.1 mm) Weight: 0.06 oz (1.8 g) Technical Specifications Sensor Technology High Precision Optical Tracking DPI (Min/Max): 1000± Buttons Number of Buttons: 8 Scrolling Hyper-Fast Scrolling Wheel Scroll Wheel: Yes, Rubber Tilt Wheel: Yes, with middle click Battery Battery life: 24 months 1Battery life may vary based on user and computing Batteries Details: 1 x AA (included) Connectivity Connection Type: 2.4 GHz wireless connection and Bluetooth Low Energy Technology Wireless range: 33 ft (10 m) (Wireless range may vary based on user, environmental and computing conditions.) Easy-Switch, 3 channels Customization app Supported by Logi Options+ on Windows and macOS (Available on Windows and macOS at logitech.com/optionsplus ) Sustainability Product carbon footprint: 5.08 kg CO2e Certified carbon neutral Warranty Information 1-Year Limited Hardware Warranty Part Number 910-004790 Compatibility Logitech Unifying receiver Required : Available USB port Windows® 10,11 or later macOS 10.5 or later ChromeOS Linux® kernel 2.6+ Bluetooth Required: Bluetooth Low Energy Technology Windows 10,11 or later macOS 10.5 or later ChromeOS Linux® kernel 2.6+ Android 5.0 or later iPadOS 13.4 or later In the Box Wireless mouse Unifying receiver 1 AA Batteries User documentation Reference Picture from Logi Options+ version 1.56.474970

This image was generated in Canva In the world of software development, efficiency and adaptability are key. A developer's choice of tools can significantly impact their productivity, the quality of their output, and their ability to efficiently work with others. Among these tools, the code editor is paramount. It is where algorithms are captured. In this blog post, we'll explore some of the industry's leading code editors, focusing on their core strengths and domains to guide you in selecting the right tool for your development needs. Visual Studio Code: A Leader Across Domains Popularity: Leading the pack Best Domain: Full-stack development, powerful in web development Where to Download: Visual Studio Code Visual Studio Code is a premier code editor developed by Microsoft. Renowned for its robust feature set, extensive plugin ecosystem, and strong community support, it is a top choice for developers across various domains. From intelligent code completion to integrated debugging tools, VS Code is a comprehensive solution that caters to developers looking for a reliable and versatile development environment. Sublime Text: The Power of Speed and Efficiency Popularity: Highly preferred Best Domain: Multi-language support, selected for rapid file editing Where to Download: Sublime Text Sublime Text stands out for its lightning-fast performance and fluid user interface. It is particularly favored by developers who must manage multiple files and projects simultaneously. Its Goto Anything feature is a significant productivity booster, allowing quick navigation to files, symbols, or lines. With its expansive API and package ecosystem, Sublime Text is a strong contender for developers seeking speed and efficiency. JupyterLab: The Data Professional's Workshop Popularity: Dominant in data science Best Domain: Interactive computing and data analysis Where to Download: JupyterLab JupyterLab is tailored for the data science community. It provides a flexible and interactive web-based interface for machine learning and statistical modeling. The ability to combine live code with narrative text, visualizations, and equations makes JupyterLab a stellar environment for collaborative data analysis and educational purposes. Android Studio: Tailor-Made for Android Developers Popularity: Unmatched for Android development Best Domain: Android application development Where to Download: Android Studio As the official integrated development environment (IDE) for Android, Android Studio is designed to streamline the app development process for this platform. It provides developers with fine-tuned tools to enhance productivity, from a rich layout editor to a comprehensive set of emulators. GNU Emacs: The Extensible, Customizable Editor Popularity: Steadfast following among experienced developers Best Domain: Versatile, with an affinity for Unix-based systems Where to Download: GNU Emacs GNU Emacs is not merely a text editor; it's an institution in the realm of coding tools. Valued for its unparalleled extensibility, Emacs can be customized to handle many tasks—from writing and editing code to reading emails and browsing the web. It's particularly well-regarded among veteran developers who appreciate its rich keyboard shortcuts and macros for streamlined coding workflows. Xcode: The Go-To for Apple Platform Development Popularity: Essential for developers in the Apple ecosystem Best Domain: iOS and macOS application development Where to Download: Xcode Xcode is Apple's official IDE for developing software for macOS, iOS, watchOS, and tvOS. It is the cornerstone of development for any Apple platform, integrating a sophisticated user interface with a comprehensive suite of tools designed to produce efficient, reliable, and practical applications. Vim: The Editor for Power Users Popularity: Consistently popular among Unix users Best Domain: Editing at speed, with keyboard-centric operations Where to Download: Vim comes pre-installed on Unix systems. For other platforms, visit the Vim Download Page. Vim is revered for its efficiency and the control it offers. It's an editor that rewards investment in learning its commands, with dividends in the form of swift navigation, extensive customizability, and a system that feels like a natural extension of the developer's thought process. While there's a steeper learning curve, the payoff is a highly optimized coding workflow. The quest for the perfect code editor is a personal one. It depends on your specific needs, preferences, and the nature of the projects you undertake. The editors listed above have proven their worth professionally and continue to be refined with each iteration. We encourage you to explore these options to discover which editor not only meets your requirements but also enhances your development strategy. Remember, the best code editor is not just a tool; it's your partner in bringing ideas to life through code.