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Embedded platform development and maintenance

Set bootargs in a PetaLinux 2019.1 Build

Dec 4, 2020
3 min

Set bootargs in a PetaLinux 2019.1 Build

This post shows how PetaLinux Tools 2019.1 lays out device tree files and how to edit bootargs. Assumptions You've installed PetaLinux Tools 2019.1 and you've built xilinx-zcu102-v2019.1-final.bsp in ~/plxprjs/xilinx-zcu102-2019.1 From a PetaLinux build directory: cd ~/plxprjs/xilinx-zcu102-2019.1 cat ./components/plnx_workspace/device-tree/device-tree/system-top.dts /* * CAUTION: This file is automatically generated by Xilinx. * Version: * Today is: Thu Nov 26 07:38:12 2020

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Zynq-7000 + AXI Slave CDMA controller on a ZC702

Sep 14, 2020
7 min

Zynq-7000 + AXI Slave CDMA controller on a ZC702

This post lists step-by-step instructions for creating an AXI slave Central Data Management Access (CDMA) controller, integrating the slave into a Zynq-7000 system using Vivado, writing a driver that exercises the CDMA, and running everything on a ZC702. More commonly referred to as DMA, DMA's are useful for passing data between a CPU (in this case, the Processing System (PS)) and external peripherals. DMA allows the PS to be idle while transfers are happening, freeing up th

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2016.4 xuartps_polled_example.c Comments and Explanation

Oct 11, 2019
10 min

2016.4 xuartps_polled_example.c Comments and Explanation

This post lists additional comments and explanation on the 2016.4 release of xuartps_polled_example.c from: https://github.com/Xilinx/embeddedsw/blob/xilinx-v2016.4/XilinxProcessorIPLib/drivers/uartps/examples/xuartps_polled_example.c Need Help? Click https://www.centennialsoftwaresolutions.com/post/import-xuartps_polled_example-c-into-a-xilinx-sdk-project if you need help bringing this example into and SDK project Comments and Additional Explanation /***********************

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Zynq-7000 + AXI Slave with Interrupt Hello World on a ZC702

May 7, 2019
5 min

Zynq-7000 + AXI Slave with Interrupt Hello World on a ZC702

This post lists step-by-step instructions for creating an AXI slave with an interrupt using Vivado HLS, integrating the slave into a Zynq-7000 system using Vivado, writing a driver that exercises the AXI slave and responds to the interrupt and running everything on a ZC702. Versions Used Xilinx Vivado 2018.2 & SDK 2018.2 Xilinx Vivado HLS 2018.2 ZC702 Rev 1.1 Windows 7 SP1 Before you Start Review the ZC702 JTAG and serial port set up instructions @ [link]. These instructions

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Grab Bag of TCP/IP Socket Create Code, Implicit Make Debug and Finding Include Paths

Jul 20, 2018
3 min

Grab Bag of TCP/IP Socket Create Code, Implicit Make Debug and Finding Include Paths

This post presents code to open and close a TCP/IP socket, a command to make it, method to find include files, commands to browse references, a command to see how the compiler was configured and a command to print implicit Make rules. Distro Ubuntu 16.04.3 Open and Close a Socket /* File socket.c */ #include <sys/socket.h> /* socket(), #define PF_INET, #define SOCK_STREAM */ #include <netinet/in.h> /* IPPROTO_TCP */ #include <stdio.h> /* fprintf (), stderr */

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