• jeromehittle

Zynq-7000 + AXI Slave CDMA controller on a ZC702


This post lists step-by-step instructions for creating an AXI slave Central Data Management Access (CDMA) controller, integrating the slave into a Zynq-7000 system using Vivado, writing a driver that exercises the CDMA, and running everything on a ZC702. More commonly referred to as DMA, DMA's are useful for passing data between a CPU (in this case, the Processing System (PS)) and external peripherals. DMA allows the PS to be idle while transfers are happening, freeing up the PS to do other things, and access the data when it's convenient for the PS to do so. Use cases include reading/writing to memory, to a radio controller, HDMI, Serial Busses, etc.

As shown in the high-level diagram below, this design uses general-purpose AXI to interface the ARM A9 processor with the CDMA, and high-performance AXI to interface the CDMA with DDR memory on a ZC702 prototype board. Pseudo-random data is stored and read back in a two transaction CDMA transfer. The returned data is compared with the sent data to verify the CDMA transaction completed successfully.


Credit: Xilinx

Versions Used


Xilinx Vivado 2018.2 & SDK 2018.2

ZC702 Rev 1.1

Windows 10 Professional v1909


Before you Start

Review the ZC702 JTAG and serial port set up instructions @ [link]. These instructions are also reviewed below.

Contents


Part 1: Create the Vivado Project

Part 2: Create the Zynq-7000 in IP Integrator

Part 3: Create the CDMA AXI Slave and Concat IP blocks

Part 4: Connect the Interrupt Lines

Part 5: Configure the PS High Performance AXI buses

Part 6: Configure the CDMA

Part 7: Automate remaining connections

Part 8: Address configuration

Part 9: Create a Top-Level HDL Wrapper

Part 10: Synthesize and Generate the Bitstream

Part 11: Export the Design and Open the SDK

Part 12: Install the USB-to-UART Driver and Get the COM Assignment

Part 13: Configure the Board to Boot from JTAG, Connect it to the PC and Power it On

Part 14: Create the Test App and BSP

Part 15: Test Debug Run + Further Config

Part 16: Test the CDMA Module


Part 1: Create the Vivado Project


Step 1:

A: Press Start

B: Expand Xilinx Design Tools


Step 2: Select Vivado 2018.2

Step 3: Select Create Project

Step 4: Click Next

Step 5:

A: Set Project name to cdmaslave

B: Set Project location to C:/vivadoprjs (create C:/vivadoprjs if it doesn't exist)

C: Click the Create project subdirectory checkbox

D: Click Next

Step 6:

A. Select RTL Project

B. Check the Do not specify sources at this time check box

C. Click Next

Step 7:

A. Click Boards

B. Type ZC702

C. Click on the ZYNQ-7 ZC702 Evaluation Board box

D. Click Next

Step 8: Click Finish


Part 2: Create the Zynq-7000 in IP Integrator


Step 1: Click Create Block Design

Step 2: Use defaults, click OK

Step 3: Click +

Step 4:

A. Type Zynq

B. Double-click on ZYNQ7 Processing System

Step 5: Click Run Block Automation

Step 6: Use defaults, click OK

You should see:


Part 3: Create the CDMA AXI Slave, Concat, and Timer IP blocks


Step 1: Click + again

Step 2:

A. Type CDMA

B. Double-click on AXI Central Direct Memory Access

You should now see:

Step 3: Click + a third time

Step 4:

A. Type concat

B. Double-click on Concat

You should now see:

Step 5: Click + one final time

Step 6:

A. Type timer

B. Double-click on AXI Timer

You should now see:


Part 4: Connect the Interrupt Lines


Step 1: Double click the ZYNQ block

Step 2: Enable IRQ_F2P[15:0]

A. Click Interrupts

B. Check the Fabric Interrupts checkbox

C. Expand the Fabric Interrupts drop-down

D. Expand the PL-PS Interrupt Ports

E. Check the IRQ_F2P[15:0] checkbox

F. Click OK

You should then see the IRQ_F2P[0:0] port on Zynq:

Step 3: Connect IRQ_F2P[0:0] to xlconcat_0 interrupt output

A: Click and hold mouse button on IRQ_F2P[0:0]

B: Drag and release mouse button on xlconcat_0 dout[1:0]

You should see:

Step 4: Connect axi timer interrupt to concatenate block

A: Click and hold mouse button on axi_timer_0 interrupt

B: Drag and release mouse button on xlconcat_0 In0[0:0]

You should see:

Step 5: Connect CDMA interrupt to concatenate block

A: Click and hold mouse button on axi_cdma_0 cdma_introut

B: Drag and release mouse button on xlconcat_0 In1[0:0]

You should see:


Part 5: Configure the PS High Performance AXI buses


Step 1: Double click the ZYNQ block

Step 2: Enable the High Performance AXI interfaces

A. Click PS-PL Configuration

B. Expand the HP Slave AXI Interface drop-down

C. Check the S AXI HP0 Interface checkbox

D. Check the S AXI HP2 Interface checkbox

E. Click OK

The PS7 should now look like this:


Part 6: Configure the CDMA


Step 1: Double click the CDMA

Step 2: Configure the CDMA

A: Uncheck Enable Scatter Gather

B: Set Write/Read Data Width to 1024

C: Set Write/Read Burst Size to 32

D: Click OK.

The CDMA IP block should now look like this:


Part 7: Automate remaining connections

Step 1: Click Run Connection Automation

The completed diagram should now look as follows:

Step 2: Click OK to close the Critical Message. We will correct the address mapping in the next section.


Part 8: Address configuration


Step 1: Select the Address Editor tab

Step 2: Adjust the high performance addresses

A: Expand axi_cdma_0

B: Expand Data

C: Adjust S_AXI_HP0 Offset Address to 0x2000_0000

D: Set S_AXI_HP0 Range to 256M

E: Adjust S_AXI_HP2 Offset Address to 0x3000_0000

F: Set S_AXI_HP2 Range to 256M


Part 9: Create a Top-Level HDL Wrapper

A. Click Sources

B. Right-click design_1 (design_1.bd) (1)

C. Click Create HDL Wrapper...