This post answers what BIF stands for (Boot Image Format) and what PDI stands for (Programmable Device Image). It also lists links to...

This post discusses the AMD Versal PMC vs. PSM. At a high level, the PMC (Platform Management Controller) controls boot, and the PSM...

This post shows how to create a Versal PLM with Vitis Classic (versions ≤2023.1, or 2023.2 when launched with the `-classic` command line...

Once you’ve created a PLM elf, the next step is to create a boot image from it, and then boot it.

Create and build a Versal PLM

Details on abbreviations, acronyms, and other terms. In this post, *O means that a component is optional and is not present in every...

Note: This post covers XCVC1902-1MSEVSVA2197, which differs from the current chip XCVC1902-2MSEVSVA2197 used on the EK-VCK190-G only in...

This blog post lists pointers to help you understand Vivado Design Tools Device Codes and AMD Part Numbers, often called Vivado Part...

The Arm SBSA Specification AMD Versal Supports The Versal ACAP Technical Reference Manual (AM011) Server Architecture lists the Arm SBSA...

This post lists links to AMD Versal third-party IP details, including vendor, version, and accessible online manuals. 3rd-Party AMD...

This page lists all Versal-related articles on the Centennial Software Solutions website. Posts which don't have a link are coming soon....

The Versal ACAP is Xilinx's latest FPGA product and is the successor to the Zynq UltraScale+. It combines an FPGA, real-time processor...