Timing Analysis Concepts & Terminology




This post presents timing analysis concepts & terminology and SDC netlist terminology. It is presented as the annotated transcript of Online Training: Part 1 - Introduction to Timing Analysis from Intel FPGA where it was originally presented. I put this together because its one of the better introductions to timing analysis concepts & terminology and I thought it may be good to extract this good info from the video.


The Video



Annotated Transcript


Timing Analyzer

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Timing Analyzer

Online Training: Part 1 - Introduction to Timing Analysis


Transcript

Welcome to the Intel Quartus Prime Software Design Series Timing Analyzer online training Part 1: Introduction to Timing Analysis.


My name is Steve.


This training is available for desktop viewing as well as in a format compatible with portable devices both available from the same link included in your registration email.


For either version while watching the training use the controls at the bottom and the side of the screen to navigate to any point.


Feel free to pause the training at any time to experiment with the software.


When you are done with the training please use the link provided in the registration email you were sent to provide us feedback on the training and ways in which it could be improved.


I'll remind you about that later.




Objectives

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Objectives

  • Perform timing analysis using the Timing Analyzer (TA) timing verification flow

  • Build Synopsys Design Constraint (SDC) files for constrining FPGA design

  • Generate timing reports inb Timing Analyzer

  • Gain familiarity with the Timing Analyzer graphical user interface (GUI)


Transcript

In this course you'll learn how to perform timing analysis in Intel Quartus Prime Software using timing analyzer.


You will use Synopsis Design Constraints or SDC files to constrain a design to meet

timing requirements and to compare results.


You will learn how to generate timer reports in timing analyzer and gain familiarity with its graphical user interface.




Agenda for Part 1

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Agenda for Part 1

  • > Timing analysis concepts & terminology <

  • > SDC netlist terminology <

  • Introduction to the Timing Analyzer GUI

  • Using Timing Analyzer

  • Incorporating timing analysis in the Intel Quartus Prime design flow

  • Timing Analyzer reporting

  • SDC constraints


Transcript

Here's the agenda for this training.


First we'll start with a look at basic timing analysis concepts and terminology used in Timing Analyzer. This will include a discussion of the terminology used to select nodes from the SDC netlist for targeting timing constraints.


Subsequent parts of this training available on the Intel training website and linked at the end of this training will introduce you to the timing analyzer GUI and its use.


You'll also learn how to incorporate timing analyzer into the Intel Quartus prime design flow, take a closer look at timing analyzers reporting features and understand the STC constraints required to fully constrain a design.




Timing Analyzer

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Timing Analyzer

  • Timing Analysis Concepts & Terminology


Transcript

Let's get started with the look at basic timing analysis concepts as well as the terminology used in the timing analyzer for constraining and validating timing requirements.




How does timing verification work?

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How does timing verification work?


Transcript

Every device path in a design must be analyzed with respect to timing specifications/requirements

  • Catch timing related errors faster than gate-level simulation & board testing

Designer must enter timing requirements & exceptions

  • Used to guide Fitter during placement & routing

  • Used to compare against actual results (post-fit)


So how does timing analyzer timing verification in the Intel Quartus Prime software work?


As you'll see the timing analyzer checks each and every path in the design with respect to the requirements specified by the designer. By looking at each and every path we can catch problems faster and easier than with gate level simulation or with board testing. The caveat is that it is up to the designer to enter timing requirements and exceptions for all paths in the design. The software knows nothing about how the design is supposed to work with respect to timing so timing constraints on all paths are required

to guide the fitter (place and router). Once the fitter has placed and routed the design the results can be compared to the original constraints to ensure that timing was met.




Timing Analysis Basic Terminology

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Timing Analysis Basic Terminology

  • Latch vs latch edges

  • Data & clock arrival time

  • Data required time

  • Setup & hold slack analysis


Transcript

Let's look at some basic timing analysis terminology that we'll use throughout this training as well as directly in the timing analyzer.




Launch & Latch Edges


Transcript

All timing analysis is based on the schematic shown here.


A source register drives a signal to a destination register.


These registers may both be contained within an FPGA design or one of them may be part of some third party device external to the FPGA on a board. Both the source and destination registers are clocked by some clock source, usually the same for both as shown here, but they could be clocked by two different sources.




Launch & Latch Edges

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Launch & Latch Edges


Launch edge: the edge with "launches" the data from the source register


Latch edge: the edge which "latches" the data at the destination register )with respect to the launch edge, selected by timing analyzer; typically 1 clock cycle, i.e. rising to rising edge.


Transcript

For a registered register path such as this the launch edge is defined as the clock edge that activates the source register. The latch edge is the clock edge that activates the destination register.


The relationship between these edges will be used to determine if register to register data

transfers will occur properly. This relationship is derived from clock constraints that will be entered by you as the designer. Also note that the data valid window, the time during which the data signal is valid on the path between the two registers opens some time after

the launch edge and closes sometime after the latch edge




Data Arrival Time

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Data Arrival Time

  • The time for data to arrive at the destination register's (REG2) D input.


Transcript

Based on the launch edge the data arrival time is defined as the time it takes for data launched from the source register by the launch edge of the clock to arrive at the D input of the destination register.




Data Arrival Time

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Data Arrival Time

  • The time for data to arrive at the destination register's (REG2) D input.


Transcript

Looking at the data arrival path defined in the diagram the data arrival time is calculated by adding the launch edge delay, adjusted to some 0 reference, the clock delay to the source register referred to as Tclk1, the clock-to-time-out or tco of the source register and the data delay between the source and destination registers which includes delays incurred by any combinational logic in the path. The data arrival time defines the start of the data valid window at the destination register and is calculated with this equation:


Equations

Data arrival time = launch edge + Tclk1 + tco + Tdata




Clock Arrival Time

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Clock Arrival Time

  • The time for the clock to arrive at destination register's (REG2) clock input.


Transcript

The clock arrival time is the time it takes for the latch edge to arrive at the destination

register's clock pin. It is equal to the latch edge adjusted to some 0 reference plus the delay from the clock source to the clock input of the destination register. If the source and destination registers are in the same clock domain the latch edge would be one clock period later with respect to the launch edge. If the clocks are coming from two different clock domains then the actual difference in time between the launch and latch edges would be used.


Equations

Clock arrival time = latch edge + Tclk2




Data Required Time (Setup Time)

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Data Required Time (Setup)

  • The minimum time required for the data to be valid before the latch edge so the data can be successfully latched into the destination register(REG2)


Transcript

The data required time is the time that a signal sent by the source register must arrive at the D input of the destination register in order to be properly sampled. This calculation ensures that data does not arrive at the destination too late with respect to the time needed for a valid synchronous transfer. Based off the latch edge and the clock arrival time the setup data required time depends on the set-up time (tsu) of the destination register, a direct function of the silicon. Data must be valid at the beginning of the setup time. the setup required time is equal to the clock arrival time minus tsu of the destination register minus an optional setup uncertainty. The setup uncertainty can be included in the calculation to help define a non-ideal clock allowing for clock jitter or a guard band.


Equations

Data required time (Setup) = Clock arrival time - tsu - Setup uncertainty (clock Jitter)

Data required time (Setup) = (latch edge + Tclk2) - tsu - Setup uncertainty (clock Jitter)




Data Required Time (Hold)

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Data Required Time (Hold)

  • The minimum time required after the latch edge for the data to remain valid for successful latching into the destination register (REG2)


Transcript

The data required time for a hold calculation is the earliest time that a new signal value can arrive at the D input of the destination register and not interfere with the data that was sampled by the previous latch edge. This calculation ensures that new data doesn't arrive too soon with respect to the time needed for a valid synchronous data transfer. Like the setup time the hold-time (th) is a function of the actual silicon. Again, based off the latch edge the hold required time is equal to the clock arrival time plus the destination register's hold time requirement. The data must remain valid until this point at which time new data can arrive at the destination. An optional hold uncertainty can be added in a similar fashion to the set-up uncertainty.


Equations

Data required time (Hold) = Clock arrival time + th + Hold uncertainty (clock jitter)

Data required time (Hold) = (latch edge + Tclk2) + th + Hold uncertainty (clock jitter)




Setup Slack (1)

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Setup Slack (1)

  • Margin by which the setup timing requirement is met

  • Ensures launched data arrives in time to meet the latching requirement


Transcript

Our ultimate goal for timing on all paths in the design is to have positive slack. Slack is a measure of how well a design is meeting or missing its timing requirements. in order for a circuit to operate properly the slack calculation must come out positive meaning there is extra margin for meeting the set-up or hold timing requirements.


Equations

Data required time (Setup) = Clock arrival time - tsu - Setup uncertainty (clock Jitter)

Data required time (Setup) = (latch edge + Tclk2) - tsu - Setup uncertainty (clock Jitter)


Setup Slack = Data actual time (Setup) - Data required time (Setup)


GOOD: positive slack

Data actual time (Setup) > Data required time (Setup)


BAD: negative slack

Data actual time (Setup) < Data required time (Setup)




Setup Slack (2)

Transcript

Thus there are two calculations performed when determining the slack: one for set-up and one for hold. By adding the clock arrival, data arrival and data required paths to the diagram we can see setup slack shown here (the green arrow). The setup slack is the difference between the data required time and the opening of the data valid window already defined as the data arrival time.


Equations

Data required time (Setup) = Clock arrival time - tsu - Setup uncertainty (clock Jitter)

Data required time (Setup) = (latch edge + Tclk2) - tsu - Setup uncertainty (clock Jitter)


Data arrival time = launch edge + Tclk1 + tco + Tdata


Setup slack = Data required time (Setup) - Data arrival time

Setup slack = ((latch edge + Tclk2) - tsu - Setup uncertainty (clock Jitter)) - (launch edge + Tclk1 + tco + Tdata)


GOOD: Setup slack positive

BAD: Setup slack negative


i.e. if the data actually arrives in less time than required, everything is good.




Hold Slack (1)

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Hold Slack (1)

  • Margin by which the hold timing requirement is met

  • Ensures latch data is not corrupted by data from the next launch edge i.e. the input data cannot change too quickly after the rising edge of the clock


Transcript

Hold slack is defined in a similar fashion.




Hold Slack (2)