Fast & Slow Corners in Timing Analysis, Steps to Run Timing

Updated: Mar 19, 2019


This post presents what fast and slow corners are and why they need to be run to correctly constrain a design. It presents the explanation given during part 2 of Timing Analyzer. In addition the steps to run Timing Analyzer are listed inline.



The Video



Featured Docs


Intel® Quartus® Prime Timing Analyzer Cookbook @ [link]



Slide-by-Slide


Online Training: Part 2 - Timing Analyzer GUI

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Timing Analyzer

Online Training: Part 2 - Timing Analyzer GUI


Transcript

Welcome to the Intel Quartus prime software design series Timing Analyzer Online Training Part 2 Timing Analyzer GUI. My name is Steve. This training is available for desktop viewing as well as in a format compatible with portable devices both available from the same link included in your registration email. For either version while watching the training use the controls at the top and side of the screen to navigate to any point. Feel free to pause the training at any time to experiment with the software. When you are done with the training

please use the link provided in the registration email you were sent to provide us feedback on the training and ways in which it can be improved. I'll remind you about that later.




Objectives

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Objectives

  • Perform timing analysis using the Timing Analyzer (TA) timing verification flow

  • Build Synopsys Design Constraint (SDC) files for constraining FPGA designs

  • Generate timing reports in Timing Analyzer

  • Gain familiarity with the Timing Analyzer graphical user interface (GUI)


Transcript

In this course you will learn how to perform timing analysis in the Intel Quartus Prime Software using Timing Analyzer. You'll use Synopsis Design Constraints or .sdc files to constrain a design to meet timing requirements and to compare results. You will learn how to

generate timer reports in timing analyzer and gain familiarity with its graphical user interface.




Agenda for Part 2

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Agenda for Part 1

  • Timing analysis concepts & terminology

  • SDC netlist terminology

  • > Introduction to the Timing Analyzer GUI <

  • > Using Timing Analyzer <

  • Incorporating timing analysis in the Intel Quartus Prime design flow

  • Timing Analyzer reporting

  • SDC constraints


Transcript

Here is the agenda for this training. In the previous part we looked at basic timing analysis

concepts and terminology used in the Timing Analyzer. This included a discussion of terminology used to select nodes from the SDC netlist for targeting timing constraints. In this part you'll be introduced to the timing analyzer GUI and its use. In subsequent parts of this

training, available on the Intel training website and linked at the end of this training, you'll learn how to incorporate timing analyzer into the Quartus Prime design flow and take a look at Timing Analyzers reporting features in more detail. Finally you'll learn about the SDC constraints required to fully constrain a design.




Introduction to the Timing Analyzer GUI

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Timing Analyzer

Introduction to the Timing Analyzer GUI


Transcript

Now that you understand all the terminology needed to use the timing analyzer, let's take a

look at the tool itself.




Timing Analyzer

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Timing Analyzer


Timing analysis engine in the Intel Quartus Prime Design Software provides a timing analysis solution for all levels of experience.


Features

Synopsys Design Constraints (SDC) support

  • Standardized constraint methodology

Easy-to-use interface

  • Constraint entry

  • Standard, on-the-fly reporting

Scripting emphasis

  • Presentation focuses on use GUI


Transcript

Timing Analyzer, found in all editions of the Intel Quartus Prime software, provides a

powerful timing analysis solution for designers with any level of timing analysis experience and for designs of all levels of complexity; is easy-to-use providing a graphical interface for beginners and those who prefer a GUI while completely supporting a Tcl scripting based environment. timing analyzer provides fast on-demand and interactive data reporting to save

time and to make it easy to get detailed timing analysis only on the paths of interest. As already mentioned Timing Analyzer uses Synopsis Design Constraints or SDC, a standard method for constraining timing in the ASIC world used by the Synopsis Primetime timing

analysis tool. Intel has adopted the SDC standard for use with PLD designs. While Tcl and SDC are command-line and text based methods of interacting with timing analyzer this training will focus on the timing analyzer GUI and show the equivalent Tcl or SDC commands.




Opening the Timing Analyzer Interface

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Opening the Timing Analyzer Interface


Toolbar button

Tools menu

Tasks window

Stand-alone mode

  • quartus_staw

Command line


Transcript

Timing Analyzer is part of the Intel Quartus Prime software but can be run independently. There are several different methods to open the timing analyzer. You can click the Timing

Analyzer toolbar button, double click in the tasks window or select Timing Analyzer from the tools menu of the Intel Quartus Prime software. You can run the Timing Analyzer GUI in standalone mode by typing quartus_staw from a command line. You can also run the Timing Analyzer without the GUI from the command line.




Timing Analyzer GUI

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Report pane

Tasks pane

View pane

Console pane


Transcript

Here is the timing analyzer GUI. It is organized similarly to the Intel Quartus Prime software with the viewing pane for viewing timing reports, a task pane for executing commonly performed tasks and a report pane for keeping track of generated timing reports. There is also an operating conditions pane for choosing different timing models. We will go over each of these parts of the window in more detail and return to each of them throughout the training.




Tasks Pane

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Tasks Pane


Provides quick access to common operations

  • Command execution

  • Report generation

Execute most commands with default settings

Use menus for non-default settings

Double-click to execute any command


Transcript

The tasks pane provides quick access to the most commonly used timing analyzer operations such as setting up the timing netlist and generating commonly used reports. When you execute a task from the task pane the task is performed with the task's default settings. This is important to remember because there may be cases when you want to perform an action that does not use the defaults. When this happens use the equivalent command from the menus at the top of the Timing Analyzer interface. the task pane operates in a similar manner to the task window in the main Intel Quartus Prime interface. To execute a command or create a report using a task pane simply double-click the item in the pane. Once a task is run the task turns green and a green checkmark is placed next to the task. Tasks can only be performed once on the current SDC timing netlist so there is no need to run them again until a new netlist is created or the design is reset. You'll see how to do this later.



Report Pane

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Report Pane


Displays list of previously generated reports current available for vewiing

  • Reports generated by Tasks pane

  • Reports generated using report commands


Transcript

The report pane displays a list of all reports that are currently available for viewing. The reports listed here may have been generated by tasks executed from the task pane or by using reporting commands directly in the console or in a script file. To view a report simply select the report. Once a report is created it is always available here until the timing netlist is reset.




View Pane

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View Pane


Main viewing area that displays report table contents & graphical results


Timing Summary table


Transcript

The View Pane is the main report viewing area of the Timing Analyzer GUI. By default newly generated reports appear in the View Pane. There are a number of different types of reports you can create that will appear here. A Timing Summary Table is the simplest and most common type of report. As mentioned, Timing Analyzer is path based meaning each and every path's timing is analyzed. Each row in a timing summary report provides basic information about either a single path in the design or about a clock domain. This information usually includes the source and destination ports or pins of the path, the launch and latch clock domains and the calculated slack for the path. Rows in the report colored black have positive slack and are meeting timing. Rows in the report colored red have negative slack indicating a timing failure.


View Pane / Timing histogram

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Timing histogram


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Other types of reports you might see are timing histograms which indicate how many paths in the design have a certain amount of slack.


View Pane / Path slack report

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Path slack report


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...and detailed path slack reports. This type of report is the most detailed type of report you can generate. It provides complete information about a single path in a design and is extremely useful in debugging timing problems.



Viewing Multiple Reports

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Click & drag '+' sign to divide view pane into multiple windows


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The view pane allows you to view multiple reports at once to make it easy to compare results. It includes a couple of special controls for this purpose. To view multiple reports at once click on the plus sign in the upper right corner of the view pane and drag it to divide the view pane into multiple windows.



Viewing Multiple Reports Example

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Viewing Multiple Reports Example


Drag bars to edges to remove splits


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Here's an example of the view pane split into four windows. To display a new report in one of the windows simply highlight a window and select report from the report pane you would like to appear in that window. You can also force report into a particular window using the red target button found in the upper right corner of a window. With a viewing pane targeted any report selected in the report pane will be placed in the targeted window. To remove windows from the view pane drag the bars between the windows to the edge. This removes the split.





Console Pane

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Console Pane


Perform direct entry and execution of SDC and Tcl commands

  • Also displays equivalent of commands executed in GUI

Displays Timing Analyzer output messages


History tab records all executed SDC & Tcl commands

  • Copy & paste to create scripts of SDC files

Run scripts from Script menu


Transcript

The console pane found at the bottom of the timing analyzer window allows you to directly enter and execute SDC or Tcl commands. Note that SDC constraints entered here do not automatically get stored in a .sdc file and will be lost if you quit the Timing Analyzer without saving. If you use the Timing Analyzer GUI to enter commands the console pane will display

the equivalent command or constraint. The Timing Analyzer console pane also displays output messages from the timing analyzer. With the history tab you can see a record of all executed SDC and Tcl commands. Just copy and paste from the history tab to easily create Tcl scripts or .sdc files.




SDC File Editor = Intel Quartus Prime Design Software text Editor

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SDC File Editor = Intel Quartus Prime Design Software text Editor

Use Intel Quartus Prime software editor to create and/or edit SDC


SDC editing unique features (for .sdc files)

  • Access to GUI dialog boxes for constraint entry (Edit > Insert Constraint)

  • Syntax coloring

  • Delimiter matches

  • Tooltip syntax help

  • Auto-complete

  • SDC templates


Transcript

To easily create and store SDC constraints the Time Analyzer feature in SDC file editor. The SDC file editor accessed through the Timing Analyzer interface by selecting a new SDC file

from the Timing Analyzer file menu is identical to the Intel Quartus Prime text editor. If you create a file using the Intel Quartus Prime text editor and give it the SDC file extension you'll have the same features available as if you created the file from within the Timing Analyzer tool. The editor includes a number of features to help you create timing constraints. If you are unfamiliar with SDC syntax you can use the insert constraints submenu found in the text

editor's edit menu to access graphical dialog boxes that will help you build valid SDC constraints. We'll see how this works next. If you are familiar with SDC and want to code your files manually syntax coloring of commands and optional arguments, detailed tooltips and highlight delimiter matching make it easy to ensure correct constraint syntax and match parentheses and square brackets. The tool also includes built in templates for quickly creating entire SDC files for common designs. We'll look at these templates in a moment.




SDC File Editor GUI Constraint Entry

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SDC File Editor GUI Constraint Entry


Construct an SDC file using Timing Analyzer graphical constraint creation tools


Constraint inserted at cursor location


Transcript

As mentioned you can use the timing analyzer graphical constraint creation tools to easily create SDC constraints. When you select a type of constraint to create from the insert constraints submenu from the SDC file editors edit menu as shown here you are presented with a dialog box that includes text fields and options for creating the constraint. As you set or change constraint options the SDC command field updates on the fly to display what the final constraint will look like. When you click the insert button the constraint is entered into the data SDC file at the cursor location. Since the constraint is entered exactly at the cursor location remember to place your cursor directly before accessing one of the dialog boxes for the constraint entry. The GUI does not add carriage returns at the end of newly created constraints so we need to add the and place a cursor correctly to avoid syntax errors.




SDC Templates

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SDC Templates


Quickly add customized constraint templates


Preview window: edit before inserting & save as user template


Transcript

Instead of manually creating SDC constraints one by one from scratch you can use SDC templates to quickly create a complete .sdc file for your design. Clicking the Insert Template